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qemu-riscv (date)
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Last Modified: Fri May 29 2020 17:12:34 -0400
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May 29, 2020
Re: [PATCH v8 49/62] target/riscv: vector widening floating-point reduction instructions
,
Alistair Francis
,
17:12
Re: [PATCH v8 48/62] target/riscv: vector single-width floating-point reduction instructions
,
Alistair Francis
,
17:10
Re: [PATCH v8 47/62] target/riscv: vector wideing integer reduction instructions
,
Alistair Francis
,
17:08
Re: [PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions
,
Alistair Francis
,
17:07
Re: [PATCH v8 45/62] target/riscv: narrowing floating-point/integer type-convert instructions
,
Alistair Francis
,
17:00
Re: [PATCH v8 44/62] target/riscv: widening floating-point/integer type-convert instructions
,
Alistair Francis
,
16:52
Re: [PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions
,
Alistair Francis
,
16:49
Re: [PATCH v8 42/62] target/riscv: vector floating-point merge instructions
,
Alistair Francis
,
16:45
Re: [PATCH v8 41/62] target/riscv: vector floating-point classify instructions
,
Alistair Francis
,
16:29
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
Alistair Francis
,
16:08
[PATCH v5 5/5] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
07:47
[PATCH v5 2/5] hw/riscv: Allow creating multiple instances of PLIC
,
Anup Patel
,
07:47
[PATCH v5 4/5] hw/riscv: spike: Allow creating multiple NUMA sockets
,
Anup Patel
,
07:47
[PATCH v5 3/5] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
,
Anup Patel
,
07:47
[PATCH v5 1/5] hw/riscv: Allow creating multiple instances of CLINT
,
Anup Patel
,
07:47
[PATCH v5 0/5] RISC-V multi-socket support
,
Anup Patel
,
07:47
Re: [PATCH v4 2/4] hw/riscv: spike: Allow creating multiple NUMA sockets
,
Anup Patel
,
05:55
Re: [PATCH v4 1/4] hw/riscv: spike: Remove deprecated ISA specific machines
,
Thomas Huth
,
01:34
May 28, 2020
[PATCH v4 4/4] docs: deprecated: Update the -bios documentation
,
Alistair Francis
,
18:25
[PATCH v4 3/4] target/riscv: Drop support for ISA spec version 1.09.1
,
Alistair Francis
,
18:25
[PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
,
Alistair Francis
,
18:25
[PATCH v4 1/4] hw/riscv: spike: Remove deprecated ISA specific machines
,
Alistair Francis
,
18:25
[PATCH v4 0/4] RISC-V: Remove deprecated ISA, CPUs and machines
,
Alistair Francis
,
18:24
[PATCH v5 10/11] riscv/opentitan: Connect the UART device
,
Alistair Francis
,
18:23
[PATCH v5 07/11] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
18:23
[PATCH v5 09/11] riscv/opentitan: Connect the PLIC device
,
Alistair Francis
,
18:23
[PATCH v5 08/11] hw/intc: Initial commit of lowRISC Ibex PLIC
,
Alistair Francis
,
18:23
[PATCH v5 11/11] target/riscv: Use a smaller guess size for no-MMU PMP
,
Alistair Francis
,
18:23
[PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
,
Alistair Francis
,
18:23
[PATCH v5 05/11] target/riscv: Add the lowRISC Ibex CPU
,
Alistair Francis
,
18:23
[PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init
,
Alistair Francis
,
18:23
[PATCH v5 03/11] target/riscv: Disable the MMU correctly
,
Alistair Francis
,
18:23
[PATCH v5 01/11] riscv/boot: Add a missing header include
,
Alistair Francis
,
18:22
[PATCH v5 02/11] target/riscv: Don't overwrite the reset vector
,
Alistair Francis
,
18:22
[PATCH v5 00/11] RISC-V Add the OpenTitan Machine
,
Alistair Francis
,
18:22
Re: [PATCH v4 03/10] target/riscv: Disable the MMU correctly
,
Alistair Francis
,
14:23
Re: [PATCH v1 2/2] sifive_e: Support the revB machine
,
Alistair Francis
,
14:23
Re: [PATCH v3 0/3] RTISC-V: Remove deprecated ISA, CPUs and machines
,
Alistair Francis
,
13:58
Re: [PATCH v4 2/4] hw/riscv: spike: Allow creating multiple NUMA sockets
,
Igor Mammedov
,
11:05
[PATCH v4 4/4] hw/riscv: virt: Allow creating multiple NUMA sockets
,
Anup Patel
,
09:30
[PATCH v4 1/4] hw/riscv: Allow creating multiple instances of CLINT
,
Anup Patel
,
09:30
[PATCH v4 3/4] hw/riscv: Allow creating multiple instances of PLIC
,
Anup Patel
,
09:30
[PATCH v4 2/4] hw/riscv: spike: Allow creating multiple NUMA sockets
,
Anup Patel
,
09:30
[PATCH v4 0/4] RISC-V multi-socket support
,
Anup Patel
,
09:30
[PATCH v2 19/24] riscv: Fix to put "riscv.hart_array" devices on sysbus
,
Markus Armbruster
,
07:05
[PATCH v2 20/24] riscv: Fix type of SiFive[EU]SocState, member parent_obj
,
Markus Armbruster
,
07:05
Re: [PATCH v3 0/3] RTISC-V: Remove deprecated ISA, CPUs and machines
,
Thomas Huth
,
01:51
RE: [PATCH v3 4/4] hw/riscv: virt: Allow creating multiple sockets
,
Anup Patel
,
00:49
May 27, 2020
Re: [PATCH v3 4/4] hw/riscv: virt: Allow creating multiple sockets
,
Atish Patra
,
23:42
Re: [PATCH v4 10/10] target/riscv: Use a smaller guess size for no-MMU PMP
,
Bin Meng
,
22:34
Re: [PATCH v4 03/10] target/riscv: Disable the MMU correctly
,
Bin Meng
,
22:32
Re: [PATCH v3 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Alistair Francis
,
16:07
Re: [PATCH v3 0/3] RTISC-V: Remove deprecated ISA, CPUs and machines
,
Alistair Francis
,
13:44
[PATCH v4 10/10] target/riscv: Use a smaller guess size for no-MMU PMP
,
Alistair Francis
,
12:59
[PATCH v4 09/10] riscv/opentitan: Connect the UART device
,
Alistair Francis
,
12:59
[PATCH v4 08/10] riscv/opentitan: Connect the PLIC device
,
Alistair Francis
,
12:59
[PATCH v4 07/10] hw/intc: Initial commit of lowRISC Ibex PLIC
,
Alistair Francis
,
12:59
[PATCH v4 06/10] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
12:59
[PATCH v4 05/10] riscv: Initial commit of OpenTitan machine
,
Alistair Francis
,
12:59
[PATCH v4 04/10] target/riscv: Add the lowRISC Ibex CPU
,
Alistair Francis
,
12:59
[PATCH v4 03/10] target/riscv: Disable the MMU correctly
,
Alistair Francis
,
12:59
[PATCH v4 01/10] riscv/boot: Add a missing header include
,
Alistair Francis
,
12:58
[PATCH v4 02/10] target/riscv: Don't overwrite the reset vector
,
Alistair Francis
,
12:58
[PATCH v4 00/10] RISC-V Add the OpenTitan Machine
,
Alistair Francis
,
12:58
Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU
,
Alistair Francis
,
12:53
[PATCH v3 4/4] hw/riscv: virt: Allow creating multiple sockets
,
Anup Patel
,
08:12
[PATCH v3 3/4] hw/riscv: Allow creating multiple instances of PLIC
,
Anup Patel
,
08:12
[PATCH v3 2/4] hw/riscv: spike: Allow creating multiple sockets
,
Anup Patel
,
08:12
[PATCH v3 1/4] hw/riscv: Allow creating multiple instances of CLINT
,
Anup Patel
,
08:12
[PATCH v3 0/4] RISC-V multi-socket support
,
Anup Patel
,
08:12
RE: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology
,
Anup Patel
,
06:55
Re: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology
,
Daniel P . Berrangé
,
06:42
RE: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology
,
Anup Patel
,
06:01
Re: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology
,
Daniel P . Berrangé
,
05:51
RE: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology
,
Anup Patel
,
05:48
Re: [PATCH v3 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Bin Meng
,
05:41
Re: [PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology
,
Daniel P . Berrangé
,
04:46
Re: [PATCH v3 0/3] RTISC-V: Remove deprecated ISA, CPUs and machines
,
Thomas Huth
,
03:17
[PATCH v2 5/5] hw/riscv: virt: Allow creating multiple sockets
,
Anup Patel
,
01:43
[PATCH v2 4/5] hw/riscv: Allow creating multiple instances of PLIC
,
Anup Patel
,
01:43
[PATCH v2 3/5] hw/riscv: spike: Allow creating multiple sockets
,
Anup Patel
,
01:43
[PATCH v2 2/5] hw/riscv: Allow creating multiple instances of CLINT
,
Anup Patel
,
01:43
[PATCH v2 1/5] hw: Add sockets_specified field in CpuTopology
,
Anup Patel
,
01:43
[PATCH v2 0/5] RISC-V multi-socket support
,
Anup Patel
,
01:43
RE: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets
,
Anup Patel
,
00:00
May 26, 2020
Re: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets
,
Alistair Francis
,
23:30
RE: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets
,
Anup Patel
,
22:55
Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU
,
LIU Zhiwei
,
21:58
Re: [PATCH v3 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Aleksandar Markovic
,
21:47
Re: [PATCH v3 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
,
Alistair Francis
,
21:00
Re: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets
,
Alistair Francis
,
20:47
Re: [PATCH v3 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Alistair Francis
,
20:33
Re: [PATCH v3 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Aleksandar Markovic
,
19:55
[PATCH v3 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Alistair Francis
,
18:55
[PATCH v3 2/3] target/riscv: Remove the deprecated CPUs
,
Alistair Francis
,
18:55
[PATCH v3 0/3] RTISC-V: Remove deprecated ISA, CPUs and machines
,
Alistair Francis
,
18:55
[PATCH v3 1/3] hw/riscv: spike: Remove deprecated ISA specific machines
,
Alistair Francis
,
18:55
Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU
,
Alistair Francis
,
13:21
Re: [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
,
Alistair Francis
,
12:59
May 22, 2020
[PATCH v4 13/13] stubs: Restrict ui/win32-kbd-hook to system-mode
,
Philippe Mathieu-Daudé
,
13:26
[PATCH v4 12/13] hw/core: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
13:26
[PATCH v4 11/13] target/s390x: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
13:26
[PATCH v4 10/13] target/i386: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
13:26
[PATCH v4 09/13] arch_init: Remove unused 'qapi-commands-misc.h' include
,
Philippe Mathieu-Daudé
,
13:26
[PATCH v4 08/13] exec: Assert CPU migration is not used on user-only build
,
Philippe Mathieu-Daudé
,
13:26
[PATCH v4 07/13] target/riscv/cpu: Restrict CPU migration to system-mode
,
Philippe Mathieu-Daudé
,
13:25
[PATCH v4 06/13] stubs/Makefile: Reduce the user-mode object list
,
Philippe Mathieu-Daudé
,
13:25
[PATCH v4 05/13] util/Makefile: Reduce the user-mode object list
,
Philippe Mathieu-Daudé
,
13:25
[PATCH v4 04/13] tests/Makefile: Restrict some softmmu-only tests
,
Philippe Mathieu-Daudé
,
13:25
[PATCH v4 03/13] tests/Makefile: Only display TCG-related tests when TCG is available
,
Philippe Mathieu-Daudé
,
13:25
[PATCH v4 02/13] configure: Avoid building TCG when not needed
,
Philippe Mathieu-Daudé
,
13:25
[PATCH v4 01/13] Makefile: Only build virtiofsd if system-mode is enabled
,
Philippe Mathieu-Daudé
,
13:25
[PATCH v4 00/13] user-mode: Prune build dependencies (part 1)
,
Philippe Mathieu-Daudé
,
13:25
Re: [PATCH v3 09/11] rules.mak: Add base-arch() rule
,
Philippe Mathieu-Daudé
,
11:15
Re: [PATCH v3 11/11] hw/semihosting: Make the feature depend of TCG, and allow to disable it
,
Philippe Mathieu-Daudé
,
11:13
Re: [PATCH v3 11/11] hw/semihosting: Make the feature depend of TCG, and allow to disable it
,
Philippe Mathieu-Daudé
,
11:11
RE: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets
,
Anup Patel
,
06:10
Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU
,
LIU Zhiwei
,
03:51
Re: [PATCH v3 11/11] hw/semihosting: Make the feature depend of TCG, and allow to disable it
,
Richard Henderson
,
00:27
Re: [PATCH v3 09/11] rules.mak: Add base-arch() rule
,
Richard Henderson
,
00:24
May 21, 2020
Re: [PATCH v3 00/11] accel: Allow targets to use Kconfig, disable semihosting by default
,
no-reply
,
22:31
Re: [PATCH v2 1/3] hw/riscv: spike: Remove deprecated ISA specific machines
,
Bin Meng
,
21:34
Re: [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
,
Alistair Francis
,
18:18
Re: [PATCH 3/4] hw/riscv: Allow creating multiple instances of PLIC
,
Alistair Francis
,
18:08
Re: [PATCH 4/4] hw/riscv: virt: Allow creating multiple sockets
,
Palmer Dabbelt
,
16:16
Re: [PATCH 3/4] hw/riscv: Allow creating multiple instances of PLIC
,
Palmer Dabbelt
,
16:16
Re: [PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets
,
Palmer Dabbelt
,
16:16
Re: [PATCH 1/4] hw/riscv: Allow creating multiple instances of CLINT
,
Palmer Dabbelt
,
16:16
[PATCH v3 11/11] hw/semihosting: Make the feature depend of TCG, and allow to disable it
,
Philippe Mathieu-Daudé
,
16:00
[PATCH v3 10/11] Makefile: Allow target-specific optional Kconfig
,
Philippe Mathieu-Daudé
,
16:00
[PATCH v3 09/11] rules.mak: Add base-arch() rule
,
Philippe Mathieu-Daudé
,
16:00
[PATCH v3 08/11] accel/Kconfig: Add the TCG selector
,
Philippe Mathieu-Daudé
,
16:00
[PATCH v3 07/11] accel/Kconfig: Extract accel selectors into their own config
,
Philippe Mathieu-Daudé
,
15:59
[PATCH v3 06/11] Makefile: Write MINIKCONF variables as one entry per line
,
Philippe Mathieu-Daudé
,
15:59
[PATCH v3 05/11] Makefile: Remove dangerous EOL trailing backslash
,
Philippe Mathieu-Daudé
,
15:59
[PATCH v3 04/11] accel/tcg: Add stub for probe_access()
,
Philippe Mathieu-Daudé
,
15:59
[PATCH v3 03/11] MAINTAINERS: Add an entry for the HAX accelerator
,
Philippe Mathieu-Daudé
,
15:59
[PATCH v3 02/11] MAINTAINERS: Add an 'overall' entry for accelerators
,
Philippe Mathieu-Daudé
,
15:59
[PATCH v3 01/11] MAINTAINERS: Fix KVM path expansion glob
,
Philippe Mathieu-Daudé
,
15:59
[PATCH v3 00/11] accel: Allow targets to use Kconfig, disable semihosting by default
,
Philippe Mathieu-Daudé
,
15:59
Re: [PATCH v2 10/10] hw/semihosting: Make the feature depend of TCG, and allow to disable it
,
Philippe Mathieu-Daudé
,
15:55
Re: [PATCH v2 09/10] Makefile: Allow target-specific optional Kconfig
,
Philippe Mathieu-Daudé
,
13:33
Re: [PATCH v1 2/2] sifive_e: Support the revB machine
,
Alistair Francis
,
12:06
Re: [PATCH] riscv: Change the default behavior if no -bios option is specified
,
Alistair Francis
,
12:02
Re: [PATCH v2 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Alistair Francis
,
11:56
Re: [PATCH v2 02/10] MAINTAINERS: Add an 'overall' entry for accelerators
,
Philippe Mathieu-Daudé
,
11:09
Re: [PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
,
Philippe Mathieu-Daudé
,
10:48
Re: [PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
,
Philippe Mathieu-Daudé
,
10:48
[PATCH 2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
,
Bin Meng
,
10:42
[PATCH 1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
,
Bin Meng
,
10:42
Re: [PATCH v8 00/62] target/riscv: support vector extension v0.7.1
,
no-reply
,
09:13
[PATCH v8 62/62] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
07:49
[PATCH v8 61/62] target/riscv: vector compress instruction
,
LIU Zhiwei
,
07:47
[PATCH v8 60/62] target/riscv: vector register gather instruction
,
LIU Zhiwei
,
07:45
[PATCH v8 59/62] target/riscv: vector slide instructions
,
LIU Zhiwei
,
07:43
[PATCH v8 58/62] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
07:41
[PATCH v8 57/62] target/riscv: integer scalar move instruction
,
LIU Zhiwei
,
07:39
[PATCH v8 56/62] target/riscv: integer extract instruction
,
LIU Zhiwei
,
07:37
[PATCH v8 55/62] target/riscv: vector element index instruction
,
LIU Zhiwei
,
07:35
[PATCH v8 54/62] target/riscv: vector iota instruction
,
LIU Zhiwei
,
07:33
[PATCH v8 53/62] target/riscv: set-X-first mask bit
,
LIU Zhiwei
,
07:31
[PATCH v8 52/62] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
07:29
[PATCH v8 51/62] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
07:27
[PATCH v8 50/62] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
07:25
[PATCH v8 49/62] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
07:23
[PATCH v8 48/62] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
07:21
[PATCH v8 47/62] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
07:19
[PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
07:17
[PATCH v8 45/62] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
07:15
[PATCH v8 44/62] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
07:13
[PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
07:11
[PATCH v8 42/62] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
07:09
[PATCH v8 41/62] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
07:07
[PATCH v8 40/62] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
07:05
[PATCH v8 39/62] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
07:03
[PATCH v8 38/62] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
07:00
[PATCH v8 37/62] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
06:58
[PATCH v8 36/62] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
06:56
[PATCH v8 35/62] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
06:54
[PATCH v8 34/62] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
06:52
[PATCH v8 33/62] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
06:50
[PATCH v8 32/62] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
06:48
[PATCH v8 31/62] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
06:46
[PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
,
LIU Zhiwei
,
06:44
[PATCH v8 29/62] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
06:42
[PATCH v8 28/62] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
06:40
[PATCH v8 27/62] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
06:38
[PATCH v8 26/62] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
06:36
[PATCH v8 25/62] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
06:34
[PATCH v8 24/62] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
06:32
[PATCH v8 23/62] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
06:30
[PATCH v8 22/62] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
06:28
[PATCH v8 21/62] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
06:26
[PATCH v8 20/62] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
06:24
[PATCH v8 19/62] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
06:22
[PATCH v8 18/62] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
06:20
[PATCH v8 17/62] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
06:18
[PATCH v8 16/62] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
06:16
[PATCH v8 15/62] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
06:14
[PATCH v8 14/62] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
06:12
[PATCH v8 13/62] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
06:10
[PATCH v8 12/62] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
06:08
[PATCH v8 11/62] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
06:06
[PATCH v8 10/62] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
06:04
[PATCH v8 09/62] target/riscv: add vector amo operations
,
LIU Zhiwei
,
06:02
[PATCH v8 08/62] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
06:00
[PATCH v8 07/62] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
05:58
[PATCH v8 06/62] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
05:56
[PATCH v8 05/62] target/riscv: add an internals.h header
,
LIU Zhiwei
,
05:54
[PATCH v8 04/62] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
05:52
[PATCH v8 03/62] target/riscv: support vector extension csr
,
LIU Zhiwei
,
05:50
[PATCH v8 02/62] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
05:48
[PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
05:46
[PATCH v8 00/62] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
05:44
[PATCH v8 02/62] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
05:42
[PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
05:21
[PATCH v8 00/62] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
05:19
May 20, 2020
Re: [PATCH v3 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
,
Bin Meng
,
21:52
Re: [PATCH v3 2/9] target/riscv: Don't overwrite the reset vector
,
Bin Meng
,
21:45
Re: [PATCH] riscv: Change the default behavior if no -bios option is specified
,
Bin Meng
,
21:37
Re: [PATCH v2 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Bin Meng
,
21:18
Re: [PATCH v2 2/3] target/riscv: Remove the deprecated CPUs
,
Bin Meng
,
21:07
Re: [PATCH v2 1/3] hw/riscv: spike: Remove deprecated ISA specific machines
,
Bin Meng
,
21:05
Re: [PATCH v1 2/2] sifive_e: Support the revB machine
,
Palmer Dabbelt
,
19:09
Re: [PATCH v1 1/2] riscv: sifive_e: Manually define the machine
,
Palmer Dabbelt
,
19:09
[PATCH v2 2/2] sifive_e: Support the revB machine
,
Alistair Francis
,
12:36
[PATCH v2 1/2] riscv: sifive_e: Manually define the machine
,
Alistair Francis
,
12:36
[PATCH v2 0/2] Add support for the HiFive1 revB
,
Alistair Francis
,
12:36
Re: [PATCH v3 1/9] riscv/boot: Add a missing header include
,
Alistair Francis
,
12:18
Re: [RFC PATCH 2/8] riscv: Generate payload scripts
,
LIU Zhiwei
,
05:06
RE: [PATCH 0/4] RISC-V multi-socket support
,
Anup Patel
,
04:50
Re: [PATCH v3 8/9] riscv/opentitan: Connect the UART device
,
Philippe Mathieu-Daudé
,
02:04
Re: [PATCH v3 7/9] riscv/opentitan: Connect the PLIC device
,
Philippe Mathieu-Daudé
,
02:03
Re: [PATCH v3 1/9] riscv/boot: Add a missing header include
,
Philippe Mathieu-Daudé
,
02:01
Re: [RFC PATCH 2/8] riscv: Generate payload scripts
,
Richard Henderson
,
01:41
Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
,
Richard Henderson
,
01:39
May 19, 2020
Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
,
LIU Zhiwei
,
22:41
Re: [RFC PATCH 2/8] riscv: Generate payload scripts
,
LIU Zhiwei
,
22:38
Re: [RFC PATCH 6/8] riscv: Add configure script
,
LIU Zhiwei
,
22:28
Re: [RFC PATCH 6/8] riscv: Add configure script
,
LIU Zhiwei
,
21:46
Re: [PATCH v2 10/10] hw/semihosting: Make the feature depend of TCG, and allow to disable it
,
Richard Henderson
,
17:44
Re: [PATCH v2 09/10] Makefile: Allow target-specific optional Kconfig
,
Richard Henderson
,
17:42
Re: [PATCH v2 04/10] accel/tcg: Add stub for probe_access()
,
Richard Henderson
,
17:41
[PATCH v3 8/9] riscv/opentitan: Connect the UART device
,
Alistair Francis
,
17:40
[PATCH v3 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
,
Alistair Francis
,
17:40
[PATCH v3 7/9] riscv/opentitan: Connect the PLIC device
,
Alistair Francis
,
17:40
[PATCH v3 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC
,
Alistair Francis
,
17:40
[PATCH v3 5/9] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
17:40
[PATCH v3 4/9] riscv: Initial commit of OpenTitan machine
,
Alistair Francis
,
17:40
[PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU
,
Alistair Francis
,
17:40
[PATCH v3 2/9] target/riscv: Don't overwrite the reset vector
,
Alistair Francis
,
17:40
[PATCH v3 0/9] RISC-V Add the OpenTitan Machine
,
Alistair Francis
,
17:40
[PATCH v3 1/9] riscv/boot: Add a missing header include
,
Alistair Francis
,
17:39
Re: [PATCH 1/4] hw/riscv: Allow creating multiple instances of CLINT
,
Alistair Francis
,
17:30
Re: [PATCH 0/4] RISC-V multi-socket support
,
Alistair Francis
,
17:29
Re: [PATCH v2 0/3] RTISC-V: Remove deprecated ISA, CPUs and machines
,
Alistair Francis
,
17:19
Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
,
Alistair Francis
,
14:12
Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description
,
LIU Zhiwei
,
08:27
Re: [RFC PATCH 0/8] RISCV risu porting
,
LIU Zhiwei
,
05:44
May 18, 2020
Re: [PATCH 19/24] riscv: Fix to put "riscv.hart_array" devices on sysbus
,
Alistair Francis
,
13:12
Re: [PATCH 20/24] riscv: Fix type of SiFive[EU]SocState, member parent_obj
,
Alistair Francis
,
13:05
Re: [PATCH v2 05/10] Makefile: Remove dangerous EOL trailing backslash
,
Alistair Francis
,
12:55
Re: [PATCH] hw: Use QEMU_IS_ALIGNED() on parallel flash block size
,
Kevin Wolf
,
09:47
Re: [PATCH] hw: Use QEMU_IS_ALIGNED() on parallel flash block size
,
Paolo Bonzini
,
08:49
Re: [PATCH] hw: Use QEMU_IS_ALIGNED() on parallel flash block size
,
Peter Maydell
,
08:42
Re: [PATCH v3 01/12] Makefile: Only build virtiofsd if system-mode is enabled
,
Dr. David Alan Gilbert
,
08:15
Re: [PATCH 20/24] riscv: Fix type of SiFive[EU]SocState, member parent_obj
,
Philippe Mathieu-Daudé
,
04:58
[PATCH 20/24] riscv: Fix type of SiFive[EU]SocState, member parent_obj
,
Markus Armbruster
,
01:04
[PATCH 19/24] riscv: Fix to put "riscv.hart_array" devices on sysbus
,
Markus Armbruster
,
01:04
May 17, 2020
Re: [PATCH v2 05/10] Makefile: Remove dangerous EOL trailing backslash
,
Thomas Huth
,
14:00
Re: [PATCH v2 02/10] MAINTAINERS: Add an 'overall' entry for accelerators
,
Thomas Huth
,
13:26
Re: [PATCH v2 01/10] MAINTAINERS: Fix KVM path expansion glob
,
Thomas Huth
,
13:23
May 16, 2020
Re: [PATCH 0/4] RISC-V multi-socket support
,
no-reply
,
07:58
Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
,
Bin Meng
,
05:03
[PATCH 4/4] hw/riscv: virt: Allow creating multiple sockets
,
Anup Patel
,
02:38
[PATCH 3/4] hw/riscv: Allow creating multiple instances of PLIC
,
Anup Patel
,
02:38
[PATCH 2/4] hw/riscv: spike: Allow creating multiple sockets
,
Anup Patel
,
02:38
[PATCH 1/4] hw/riscv: Allow creating multiple instances of CLINT
,
Anup Patel
,
02:38
[PATCH 0/4] RISC-V multi-socket support
,
Anup Patel
,
02:38
May 15, 2020
Re: [PATCH v2 00/10] accel: Allow targets to use Kconfig, disable semihosting by default
,
no-reply
,
23:59
Re: [PATCH v2 00/10] accel: Allow targets to use Kconfig, disable semihosting by default
,
no-reply
,
23:45
Re: [PATCH v2 5/9] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
15:55
Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
,
Alistair Francis
,
15:52
[PATCH v2 10/10] hw/semihosting: Make the feature depend of TCG, and allow to disable it
,
Philippe Mathieu-Daudé
,
13:09
[PATCH v2 09/10] Makefile: Allow target-specific optional Kconfig
,
Philippe Mathieu-Daudé
,
13:09
[PATCH v2 08/10] accel/Kconfig: Add the TCG selector
,
Philippe Mathieu-Daudé
,
13:09
[PATCH v2 07/10] accel/Kconfig: Extract accel selectors into their own config
,
Philippe Mathieu-Daudé
,
13:08
[PATCH v2 06/10] Makefile: Write MINIKCONF variables as one entry per line
,
Philippe Mathieu-Daudé
,
13:08
[PATCH v2 05/10] Makefile: Remove dangerous EOL trailing backslash
,
Philippe Mathieu-Daudé
,
13:08
[PATCH v2 04/10] accel/tcg: Add stub for probe_access()
,
Philippe Mathieu-Daudé
,
13:08
[PATCH v2 03/10] MAINTAINERS: Add an entry for the HAX accelerator
,
Philippe Mathieu-Daudé
,
13:08
[PATCH v2 02/10] MAINTAINERS: Add an 'overall' entry for accelerators
,
Philippe Mathieu-Daudé
,
13:08
[PATCH v2 01/10] MAINTAINERS: Fix KVM path expansion glob
,
Philippe Mathieu-Daudé
,
13:08
[PATCH v2 00/10] accel: Allow targets to use Kconfig, disable semihosting by default
,
Philippe Mathieu-Daudé
,
13:08
Re: [PATCH v2 5/9] hw/char: Initial commit of Ibex UART
,
Philippe Mathieu-Daudé
,
03:28
Re: [PATCH v2 5/9] hw/char: Initial commit of Ibex UART
,
Philippe Mathieu-Daudé
,
03:26
Re: [PATCH v2 8/9] riscv/opentitan: Connect the UART device
,
Bin Meng
,
02:29
Re: [PATCH v2 7/9] riscv/opentitan: Connect the PLIC device
,
Bin Meng
,
02:29
Re: [PATCH v2 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
,
Bin Meng
,
02:29
Re: [PATCH v2 4/9] riscv: Initial commit of OpenTitan machine
,
Bin Meng
,
01:14
Re: [PATCH v2 1/9] riscv/boot: Add a missing header include
,
Bin Meng
,
01:00
Re: [PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU
,
Bin Meng
,
00:57
Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
,
Bin Meng
,
00:54
May 14, 2020
Re: [PATCH v2 5/9] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
18:08
Re: [PATCH v2 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC
,
Alistair Francis
,
18:01
Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
,
Alistair Francis
,
17:51
[PATCH v1 2/2] sifive_e: Support the revB machine
,
Alistair Francis
,
16:55
[PATCH v1 1/2] riscv: sifive_e: Manually define the machine
,
Alistair Francis
,
16:55
Re: [PATCH v2 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC
,
Philippe Mathieu-Daudé
,
14:40
Re: [PATCH v2 5/9] hw/char: Initial commit of Ibex UART
,
Philippe Mathieu-Daudé
,
14:00
Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
,
Philippe Mathieu-Daudé
,
13:54
Re: [PATCH v2 1/9] riscv/boot: Add a missing header include
,
Philippe Mathieu-Daudé
,
13:51
Re: [PATCH v2 1/9] riscv/boot: Add a missing header include
,
Bin Meng
,
11:46
Re: [PATCH v2 1/9] riscv/boot: Add a missing header include
,
Alistair Francis
,
11:38
Re: [PATCH v2 1/9] riscv/boot: Add a missing header include
,
Bin Meng
,
11:34
May 13, 2020
Re: [PATCH v2 0/9] RISC-V Add the OpenTitan Machine
,
Alistair Francis
,
14:27
May 12, 2020
Re: [PATCH] hw: Use QEMU_IS_ALIGNED() on parallel flash block size
,
Alistair Francis
,
11:03
Re: [PATCH 08/11] target/s390x: Restrict system-mode declarations
,
David Hildenbrand
,
02:52
Re: [PATCH 08/11] target/s390x: Restrict system-mode declarations
,
Philippe Mathieu-Daudé
,
02:46
Re: [PATCH 08/11] target/s390x: Restrict system-mode declarations
,
Cornelia Huck
,
02:02
May 11, 2020
[PATCH] hw: Use QEMU_IS_ALIGNED() on parallel flash block size
,
Philippe Mathieu-Daudé
,
16:53
Re: [RFC PATCH 7/8] riscv: Add RV64M instructions description
,
Richard Henderson
,
14:12
Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description
,
Richard Henderson
,
14:11
Re: [RFC PATCH 4/8] riscv: Implement payload load interfaces
,
Richard Henderson
,
14:07
Re: [RFC PATCH 6/8] riscv: Add configure script
,
Richard Henderson
,
14:06
Re: [RFC PATCH 5/8] riscv: Add standard test case
,
Richard Henderson
,
14:04
Re: [RFC PATCH 4/8] riscv: Implement payload load interfaces
,
Richard Henderson
,
14:03
Re: [RFC PATCH 3/8] riscv: Define riscv struct reginfo
,
Richard Henderson
,
13:42
Re: [RFC PATCH 2/8] riscv: Generate payload scripts
,
Richard Henderson
,
13:41
Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
,
Richard Henderson
,
12:39
Re: [RFC PATCH 0/8] RISCV risu porting
,
Richard Henderson
,
12:30
Re: [PATCH 08/11] target/s390x: Restrict system-mode declarations
,
Philippe Mathieu-Daudé
,
08:21
Re: [PATCH 08/11] target/s390x: Restrict system-mode declarations
,
Cornelia Huck
,
06:48
Re: [PATCH 07/11] target/s390x/helper: Clean ifdef'ry
,
Cornelia Huck
,
06:44
Re: [PATCH 06/11] target/s390x: Only compile decode_basedisp() on system-mode
,
Cornelia Huck
,
06:39
Re: [PATCH 04/11] sysemu/hvf: Only declare hvf_allowed when HVF is available
,
Cornelia Huck
,
06:23
Re: [PATCH 03/11] sysemu/tcg: Only declare tcg_allowed when TCG is available
,
Cornelia Huck
,
06:20
Re: [PATCH 02/11] sysemu/accel: Restrict machine methods to system-mode
,
Cornelia Huck
,
06:18
Re: [PATCH 02/11] sysemu/accel: Restrict machine methods to system-mode
,
Edgar E. Iglesias
,
05:54
Re: [PATCH 04/11] sysemu/hvf: Only declare hvf_allowed when HVF is available
,
Edgar E. Iglesias
,
05:47
Re: [PATCH 03/11] sysemu/tcg: Only declare tcg_allowed when TCG is available
,
Edgar E. Iglesias
,
05:46
Re: [PATCH 07/11] target/s390x/helper: Clean ifdef'ry
,
David Hildenbrand
,
05:44
May 10, 2020
Re: [PATCH 09/11] target/cpu: Restrict handlers using hwaddr type to system-mode
,
David Gibson
,
21:18
Re: [PATCH 05/11] target/ppc: Restrict PPCVirtualHypervisorClass to system-mode
,
David Gibson
,
21:18
Re: [PATCH 01/11] plugins: Restrict functions handling hwaddr to system-mode
,
Philippe Mathieu-Daudé
,
06:44
May 09, 2020
Re: [PATCH 09/11] target/cpu: Restrict handlers using hwaddr type to system-mode
,
Paolo Bonzini
,
17:03
Re: [PATCH 09/11] target/cpu: Restrict handlers using hwaddr type to system-mode
,
Philippe Mathieu-Daudé
,
16:01
Re: [PATCH 09/11] target/cpu: Restrict handlers using hwaddr type to system-mode
,
Philippe Mathieu-Daudé
,
12:08
[PATCH 11/11] exec/cpu-common: Poison hwaddr type in user-mode emulation
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 10/11] exec: Use 'cpu-common.h' instead of system-mode specific 'hwaddr.h'
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 09/11] target/cpu: Restrict handlers using hwaddr type to system-mode
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 08/11] target/s390x: Restrict system-mode declarations
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 07/11] target/s390x/helper: Clean ifdef'ry
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 06/11] target/s390x: Only compile decode_basedisp() on system-mode
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 05/11] target/ppc: Restrict PPCVirtualHypervisorClass to system-mode
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 04/11] sysemu/hvf: Only declare hvf_allowed when HVF is available
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 03/11] sysemu/tcg: Only declare tcg_allowed when TCG is available
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 02/11] sysemu/accel: Restrict machine methods to system-mode
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 01/11] plugins: Restrict functions handling hwaddr to system-mode
,
Philippe Mathieu-Daudé
,
09:09
[PATCH 00/11] exec/cpu: Poison 'hwaddr' type in user-mode emulation
,
Philippe Mathieu-Daudé
,
09:09
May 08, 2020
Re: [PATCH v3 00/12] user-mode: Prune build dependencies (part 1)
,
Philippe Mathieu-Daudé
,
12:24
May 07, 2020
[PATCH v2 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
,
Alistair Francis
,
15:21
[PATCH v2 8/9] riscv/opentitan: Connect the UART device
,
Alistair Francis
,
15:21
[PATCH v2 7/9] riscv/opentitan: Connect the PLIC device
,
Alistair Francis
,
15:21
[PATCH v2 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC
,
Alistair Francis
,
15:21
[PATCH v2 5/9] hw/char: Initial commit of Ibex UART
,
Alistair Francis
,
15:21
[PATCH v2 4/9] riscv: Initial commit of OpenTitan machine
,
Alistair Francis
,
15:21
[PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU
,
Alistair Francis
,
15:21
[PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
,
Alistair Francis
,
15:21
[PATCH v2 1/9] riscv/boot: Add a missing header include
,
Alistair Francis
,
15:21
[PATCH v2 0/9] RISC-V Add the OpenTitan Machine
,
Alistair Francis
,
15:21
Re: [PATCH v1 2/2] target/riscv: Drop support for ISA spec version 1.09.1
,
Alistair Francis
,
15:20
[PATCH v2 3/3] target/riscv: Drop support for ISA spec version 1.09.1
,
Alistair Francis
,
15:19
[PATCH v2 2/3] target/riscv: Remove the deprecated CPUs
,
Alistair Francis
,
15:19
[PATCH v2 1/3] hw/riscv: spike: Remove deprecated ISA specific machines
,
Alistair Francis
,
15:19
[PATCH v2 0/3] RTISC-V: Remove deprecated ISA, CPUs and machines
,
Alistair Francis
,
15:19
May 06, 2020
Re: [PATCH v2] target/riscv: fix check of guest pa top bits
,
Alistair Francis
,
17:16
Re: [PATCH] riscv: Change the default behavior if no -bios option is specified
,
Alistair Francis
,
17:02
Re: [PATCH v1 2/2] target/riscv: Drop support for ISA spec version 1.09.1
,
Philippe Mathieu-Daudé
,
08:11
Re: [PATCH v1 1/2] hw/riscv: spike: Remove deprecated ISA specific machines
,
Philippe Mathieu-Daudé
,
08:05
Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Bin Meng
,
06:00
May 05, 2020
Re: [PATCH] riscv: Change the default behavior if no -bios option is specified
,
Bin Meng
,
21:34
[PATCH v1 2/2] target/riscv: Drop support for ISA spec version 1.09.1
,
Alistair Francis
,
21:20
[PATCH v1 1/2] hw/riscv: spike: Remove deprecated ISA specific machines
,
Alistair Francis
,
21:20
[PATCH v1 0/2] RTISC-V: Remove deprecated ISA, CPUs and machines
,
Alistair Francis
,
21:20
Re: [PATCH] riscv: Change the default behavior if no -bios option is specified
,
Alistair Francis
,
18:37
Re: [PATCH v2] target/riscv: fix check of guest pa top bits
,
Alistair Francis
,
16:49
Re: [PATCH] riscv: Change the default behavior if no -bios option is specified
,
Alistair Francis
,
16:42
Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Alistair Francis
,
16:03
Re: [PATCH v3 11/12] target/s390x: Restrict CpuClass::get_crash_info() to system-mode
,
Cornelia Huck
,
08:05
Re: [PATCH v3 00/12] user-mode: Prune build dependencies (part 1)
,
Laurent Vivier
,
04:34
Re: [PATCH v3 00/12] user-mode: Prune build dependencies (part 1)
,
no-reply
,
04:33
May 04, 2020
Re: [PATCH 4/5] riscv/spike: Change the default bios to use generic platform image
,
Alistair Francis
,
12:03
Re: [PATCH 3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Alistair Francis
,
12:02
Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Alistair Francis
,
12:00
Re: [PATCH v3 08/12] exec: Assert CPU migration is not used on user-only build
,
Alistair Francis
,
11:50
Re: [PATCH v3 02/12] configure: Avoid building TCG when not needed
,
Alistair Francis
,
11:49
[PATCH v3 12/12] hw/core: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
11:30
[PATCH v3 11/12] target/s390x: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
11:30
[PATCH v3 10/12] target/i386: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
11:30
[PATCH v3 09/12] arch_init: Remove unused 'qapi-commands-misc.h' include
,
Philippe Mathieu-Daudé
,
11:30
[PATCH v3 08/12] exec: Assert CPU migration is not used on user-only build
,
Philippe Mathieu-Daudé
,
11:30
[PATCH v3 07/12] target/riscv/cpu: Restrict CPU migration to system-mode
,
Philippe Mathieu-Daudé
,
11:30
[PATCH v3 06/12] stubs/Makefile: Reduce the user-mode object list
,
Philippe Mathieu-Daudé
,
11:29
[PATCH v3 05/12] util/Makefile: Reduce the user-mode object list
,
Philippe Mathieu-Daudé
,
11:29
[PATCH v3 04/12] tests/Makefile: Restrict some softmmu-only tests
,
Philippe Mathieu-Daudé
,
11:29
[PATCH v3 03/12] tests/Makefile: Only display TCG-related tests when TCG is available
,
Philippe Mathieu-Daudé
,
11:29
[PATCH v3 02/12] configure: Avoid building TCG when not needed
,
Philippe Mathieu-Daudé
,
11:29
[PATCH v3 01/12] Makefile: Only build virtiofsd if system-mode is enabled
,
Philippe Mathieu-Daudé
,
11:29
[PATCH v3 00/12] user-mode: Prune build dependencies (part 1)
,
Philippe Mathieu-Daudé
,
11:29
Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Anup Patel
,
04:17
Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Bin Meng
,
04:05
Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Bin Meng
,
04:00
Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Anup Patel
,
03:52
Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Bin Meng
,
03:17
May 03, 2020
Re: [PATCH 5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware()
,
Anup Patel
,
00:44
Re: [PATCH 3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Anup Patel
,
00:43
Re: [PATCH 4/5] riscv/spike: Change the default bios to use generic platform image
,
Anup Patel
,
00:42
Re: [PATCH 2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform
,
Anup Patel
,
00:41
Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Anup Patel
,
00:39
May 01, 2020
Re: [PATCH] target/riscv: fix check of guest pa top bits
,
Jonathan Behrens
,
15:15
Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS
,
Jose Martins
,
14:57
Re: [PATCH] target/riscv: fix check of guest pa top bits
,
Jose Martins
,
14:54
[PATCH v2] target/riscv: fix check of guest pa top bits
,
Jose Martins
,
14:51
[PATCH 4/5] riscv/spike: Change the default bios to use generic platform image
,
Bin Meng
,
11:51
[PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform
,
Bin Meng
,
11:51
[PATCH 2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform
,
Bin Meng
,
11:51
[PATCH 3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u
,
Bin Meng
,
11:51
[PATCH 5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware()
,
Bin Meng
,
11:51
[PATCH 0/5] riscv: Switch to use generic platform of opensbi bios images
,
Bin Meng
,
11:51
RE: [PATCH] riscv/spike: Change the default bios to use plain binary image
,
Anup Patel
,
08:47
Re: [PATCH] riscv/spike: Change the default bios to use plain binary image
,
Bin Meng
,
08:44
Re: [PATCH] riscv/spike: Change the default bios to use plain binary image
,
Anup Patel
,
08:41
[PATCH] riscv/spike: Change the default bios to use plain binary image
,
Bin Meng
,
08:30
[PATCH] riscv: Change the default behavior if no -bios option is specified
,
Bin Meng
,
08:20
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