[PATCH v2 2/9] target/riscv: Don't overwrite the reset vector

qemu-riscv

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[PATCH v2 2/9] target/riscv: Don't overwrite the reset vector

From:	Alistair Francis
Subject:	[PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
Date:	Thu, 7 May 2020 12:13:04 -0700

If the reset vector is set in the init function don't set it again in
realise.

Signed-off-by: Alistair Francis <address@hidden>
---
 target/riscv/cpu.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..8f837edf8d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -111,6 +111,14 @@ static void set_feature(CPURISCVState *env, int feature)
     env->features |= (1ULL << feature);
 }
 
+static int get_resetvec(CPURISCVState *env)
+{
+#ifndef CONFIG_USER_ONLY
+    return env->resetvec;
+#endif
+    return 0;
+}
+
 static void set_resetvec(CPURISCVState *env, int resetvec)
 {
 #ifndef CONFIG_USER_ONLY
@@ -123,7 +131,6 @@ static void riscv_any_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_11_0);
-    set_resetvec(env, DEFAULT_RSTVEC);
 }
 
 #if defined(TARGET_RISCV32)
@@ -140,7 +147,6 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_09_1);
-    set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
     set_feature(env, RISCV_FEATURE_PMP);
 }
@@ -150,7 +156,6 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
     set_feature(env, RISCV_FEATURE_PMP);
 }
@@ -160,7 +165,6 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_PMP);
 }
 
@@ -169,7 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_PMP);
 }
 
@@ -187,7 +190,6 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_09_1);
-    set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
     set_feature(env, RISCV_FEATURE_PMP);
 }
@@ -197,7 +199,6 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
     set_feature(env, RISCV_FEATURE_PMP);
 }
@@ -207,7 +208,6 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_PMP);
 }
 
@@ -399,7 +399,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
     }
 
     set_priv_version(env, priv_version);
-    set_resetvec(env, DEFAULT_RSTVEC);
+    if (!get_resetvec(env)) {
+        set_resetvec(env, DEFAULT_RSTVEC);
+    }
 
     if (cpu->cfg.mmu) {
         set_feature(env, RISCV_FEATURE_MMU);
-- 
2.26.2

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[PATCH v2 0/9] RISC-V Add the OpenTitan Machine, Alistair Francis, 2020/05/07
- [PATCH v2 1/9] riscv/boot: Add a missing header include, Alistair Francis, 2020/05/07
  - Re: [PATCH v2 1/9] riscv/boot: Add a missing header include, Bin Meng, 2020/05/14
    - Re: [PATCH v2 1/9] riscv/boot: Add a missing header include, Alistair Francis, 2020/05/14
    - Re: [PATCH v2 1/9] riscv/boot: Add a missing header include, Bin Meng, 2020/05/14
    - Re: [PATCH v2 1/9] riscv/boot: Add a missing header include, Philippe Mathieu-Daudé, 2020/05/14
    - Re: [PATCH v2 1/9] riscv/boot: Add a missing header include, Bin Meng, 2020/05/15
- [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis <=
  - Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Philippe Mathieu-Daudé, 2020/05/14
    - Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/14
    - Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Bin Meng, 2020/05/15
    - Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/15
    - Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Bin Meng, 2020/05/16
    - Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/19
- [PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/05/07
  - Re: [PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU, Bin Meng, 2020/05/15
- [PATCH v2 4/9] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/05/07
  - Re: [PATCH v2 4/9] riscv: Initial commit of OpenTitan machine, Bin Meng, 2020/05/15

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