[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 1/9] riscv/boot: Add a missing header include
|
From: |
Bin Meng |
|
Subject: |
Re: [PATCH v2 1/9] riscv/boot: Add a missing header include |
|
Date: |
Fri, 15 May 2020 13:00:08 +0800 |
Hi Alistair,
On Thu, May 14, 2020 at 11:38 PM Alistair Francis <address@hidden> wrote:
>
> On Thu, May 14, 2020 at 8:34 AM Bin Meng <address@hidden> wrote:
> >
> > On Fri, May 8, 2020 at 3:24 AM Alistair Francis
> > <address@hidden> wrote:
> > >
> > > Signed-off-by: Alistair Francis <address@hidden>
> > > ---
> > > include/hw/riscv/boot.h | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> > > index 474a940ad5..9daa98da08 100644
> > > --- a/include/hw/riscv/boot.h
> > > +++ b/include/hw/riscv/boot.h
> > > @@ -21,6 +21,7 @@
> > > #define RISCV_BOOT_H
> > >
> > > #include "exec/cpu-defs.h"
> > > +#include "hw/loader.h"
> >
> > Why is this needed? Currently this does not break build.
>
> Currently every c file that includes boot.h also includes loader.h
> before it. Which is why the build works fine. We should be able to
> include just boot.h though so this is a small fixup to allow that.
>
Please include such in the commit message to help people understand.
Reviewed-by: Bin Meng <address@hidden>
Regards,
Bin
[PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/07
- Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Philippe Mathieu-Daudé, 2020/05/14
- Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/14
- Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Bin Meng, 2020/05/15
- Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/15
- Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Bin Meng, 2020/05/16
- Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/19
[PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/05/07
[PATCH v2 4/9] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/05/07