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Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description
From: |
Richard Henderson |
Subject: |
Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description |
Date: |
Mon, 11 May 2020 11:11:31 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 |
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
> +
> +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
> +
> +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
> +
> +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
Interesting question here: Do we really want to avoid the reserved rounding
modes, or do we want to verify that we raise an invalid operand exception?
I guess I'm fine with it either way.
r~
- Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description,
Richard Henderson <=