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[PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init
From: |
Alistair Francis |
Subject: |
[PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init |
Date: |
Thu, 28 May 2020 15:14:17 -0700 |
The PMP is enabled by default via the "pmp" property so there is no need
for us to set it in the init function. As all CPUs have PMP support just
remove the set_feature() call in the CPU init functions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8deba3d16d..406e8f37d7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -142,7 +142,6 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_09_1);
set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_PMP);
}
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
@@ -151,7 +150,6 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_PMP);
}
static void rv32imacu_nommu_cpu_init(Object *obj)
@@ -160,7 +158,6 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_PMP);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -170,7 +167,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_PMP);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -190,7 +186,6 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_09_1);
set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_PMP);
}
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
@@ -199,7 +194,6 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_PMP);
}
static void rv64imacu_nommu_cpu_init(Object *obj)
@@ -208,7 +202,6 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_PMP);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
--
2.26.2
- [PATCH v5 00/11] RISC-V Add the OpenTitan Machine, Alistair Francis, 2020/05/28
- [PATCH v5 02/11] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/28
- [PATCH v5 01/11] riscv/boot: Add a missing header include, Alistair Francis, 2020/05/28
- [PATCH v5 03/11] target/riscv: Disable the MMU correctly, Alistair Francis, 2020/05/28
- [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init,
Alistair Francis <=
- [PATCH v5 05/11] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/05/28
- [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/05/28
- [PATCH v5 11/11] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/05/28
- [PATCH v5 08/11] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/05/28
- [PATCH v5 09/11] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/05/28
- [PATCH v5 07/11] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/05/28
- [PATCH v5 10/11] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/05/28