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[PATCH v3 2/9] target/riscv: Don't overwrite the reset vector
From: |
Alistair Francis |
Subject: |
[PATCH v3 2/9] target/riscv: Don't overwrite the reset vector |
Date: |
Tue, 19 May 2020 14:31:29 -0700 |
The reset vector is set in the init function don't set it again in
realize.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..5eb3c02735 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -133,6 +133,7 @@ static void riscv_base32_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
+ set_resetvec(env, DEFAULT_RSTVEC);
}
static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
@@ -180,6 +181,7 @@ static void riscv_base64_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
+ set_resetvec(env, DEFAULT_RSTVEC);
}
static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
@@ -399,7 +401,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_priv_version(env, priv_version);
- set_resetvec(env, DEFAULT_RSTVEC);
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
--
2.26.2
[PATCH v3 4/9] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/05/19
[PATCH v3 5/9] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/05/19
[PATCH v3 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/05/19
[PATCH v3 7/9] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/05/19