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[PATCH v4 01/10] riscv/boot: Add a missing header include
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From: |
Alistair Francis |
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Subject: |
[PATCH v4 01/10] riscv/boot: Add a missing header include |
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Date: |
Wed, 27 May 2020 09:50:14 -0700 |
As the functions declared in this header use the symbol_fn_t
typedef itself declared in "hw/loader.h", we need to include
it here to make the header file self-contained.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
---
include/hw/riscv/boot.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 474a940ad5..9daa98da08 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -21,6 +21,7 @@
#define RISCV_BOOT_H
#include "exec/cpu-defs.h"
+#include "hw/loader.h"
void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
--
2.26.2
- [PATCH v4 00/10] RISC-V Add the OpenTitan Machine, Alistair Francis, 2020/05/27
- [PATCH v4 02/10] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/27
- [PATCH v4 01/10] riscv/boot: Add a missing header include,
Alistair Francis <=
- [PATCH v4 03/10] target/riscv: Disable the MMU correctly, Alistair Francis, 2020/05/27
- [PATCH v4 04/10] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/05/27
- [PATCH v4 05/10] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/05/27
- [PATCH v4 06/10] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/05/27
- [PATCH v4 07/10] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/05/27
- [PATCH v4 08/10] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/05/27
- [PATCH v4 09/10] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/05/27
- [PATCH v4 10/10] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/05/27