Re: [RFC PATCH 0/8] RISCV risu porting

[LIU Zhiwei]

On 2020/5/12 0:30, Richard Henderson wrote:

> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> > It's some difficult when I try to support RV32, because it's very
> > similiar to RV64, so I can't make two .risu files like arm.risu and
> > aarch64.risu.
> >       
> You could a command-line parameter, like --be or --sve for this.
>     
    Yes. I should add a "--xlen" parameter to specify the general
    register length in risugen_riscv.pm.
    
    Besides, I should modify current riscv64.risu.
    
    For instructions in RV32 and RV64:
LB RV32_64 imm:12 rs1:5 000 rd:5 0000011
    For RV64 only instructions:
LD RV64 imm:12 rs1:5 011 rd:5 0000011 
    So I can  generate RV32 instructions through  --pattern '*.RV32.*',
    and the  RV64 instructions through --pattern '.*RV64.*'.
    
    Best Regards,
    Zhiwei
> r~
>