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[Qemu-ppc] [PATCH v3 14/24] target-ppc: Move POWER7/8 SPR registration t
From: |
Alexey Kardashevskiy |
Subject: |
[Qemu-ppc] [PATCH v3 14/24] target-ppc: Move POWER7/8 SPR registration to helpers |
Date: |
Tue, 27 May 2014 20:37:26 +1000 |
This puts SPRs into groups and moves their registration
to group helpers.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
target-ppc/translate_init.c | 161 +++++++++++++++++++++++---------------------
1 file changed, 85 insertions(+), 76 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8e1b465..ca592ed 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7498,6 +7498,82 @@ static void gen_spr_970_lpar(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_book3s_ids(CPUPPCState *env)
+{
+ /* Processor identification */
+ spr_register(env, SPR_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_purr(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
+ spr_register_kvm(env, SPR_PURR, "PURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ KVM_REG_PPC_PURR, 0x00000000);
+ spr_register_kvm(env, SPR_SPURR, "SPURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ KVM_REG_PPC_SPURR, 0x00000000);
+#endif
+}
+
+static void gen_spr_power6_dbg(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_CFAR, "SPR_CFAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_cfar, &spr_write_cfar,
+ 0x00000000);
+#endif
+}
+
+static void gen_spr_book3s_common(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSCR, 0x00000000);
+#endif
+ spr_register(env, SPR_CTRL, "SPR_CTRLT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x80800000);
+ spr_register(env, SPR_UCTRL, "SPR_CTRLF",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x80800000);
+ spr_register(env, SPR_PPR, "PPR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_pcr(CPUPPCState *env)
+{
+ /*
+ * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
+ * POWERPC_EXCP_INVAL_SPR.
+ */
+ spr_register(env, SPR_PCR, "PCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ 0x00000000);
+}
+
+static void gen_spr_power8_branch_control(CPUPPCState *env)
+{
+ spr_register(env, SPR_TAR, "TAR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
static void init_proc_POWER(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -7709,67 +7785,16 @@ static void init_proc_POWER7 (CPUPPCState *env)
{
gen_spr_ne_601(env);
gen_spr_7xx(env);
- /* Time base */
+ gen_spr_book3s_altivec(env);
gen_tbl(env);
- /* Processor identification */
- spr_register(env, SPR_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
-#if !defined(CONFIG_USER_ONLY)
- /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
- spr_register_kvm(env, SPR_PURR, "PURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- KVM_REG_PPC_PURR, 0x00000000);
- spr_register_kvm(env, SPR_SPURR, "SPURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- KVM_REG_PPC_SPURR, 0x00000000);
- spr_register(env, SPR_CFAR, "SPR_CFAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_cfar, &spr_write_cfar,
- 0x00000000);
- spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DSCR, 0x00000000);
- spr_register_kvm(env, SPR_POWER_MMCRA, "SPR_MMCRA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCRA, 0x00000000);
- spr_register_kvm(env, SPR_7XX_PMC5, "SPR_7XX_PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC5, 0x00000000);
- spr_register_kvm(env, SPR_7XX_PMC6, "SPR_7XX_PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC6, 0x00000000);
-#endif /* !CONFIG_USER_ONLY */
+ gen_spr_book3s_ids(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_book3s_common(env);
+ gen_spr_book3s_pmu(env);
+ gen_spr_book3s_lpar(env);
+ gen_spr_book3s_pcr(env);
+ gen_spr_power6_dbg(env);
gen_spr_amr(env);
- /* XXX : not implemented */
- spr_register(env, SPR_CTRL, "SPR_CTRLT",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x80800000);
- spr_register(env, SPR_UCTRL, "SPR_CTRLF",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x80800000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_PPR, "PPR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Logical partitionning */
- spr_register_kvm(env, SPR_LPCR, "LPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, 0x00000000);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
@@ -7779,18 +7804,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
/* Allocate hardware IRQ controller */
ppcPOWER7_irq_init(env);
- /* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
- vscr_init(env, 0x00010000);
-
- /*
- * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
- * POWERPC_EXCP_INVAL_SPR.
- */
- spr_register(env, SPR_PCR, "PCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- 0x00000000);
}
POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
@@ -7920,11 +7933,7 @@ static void init_proc_POWER8(CPUPPCState *env)
/* inherit P7 */
init_proc_POWER7(env);
- /* P8 supports the TAR */
- spr_register(env, SPR_TAR, "TAR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ gen_spr_power8_branch_control(env);
}
POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
--
1.8.4.rc4
- [Qemu-ppc] [PATCH v3 09/24] target-ppc: Add HID4 SPR for PPC970, (continued)
- [Qemu-ppc] [PATCH v3 09/24] target-ppc: Add HID4 SPR for PPC970, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 11/24] target-ppc: Remove check_pow_970FX, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 13/24] target-ppc: Enable PMU SPRs migration, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 15/24] target-ppc: Refactor class init for POWER7/8, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 19/24] target-ppc: Add POWER8's TM SPRs, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 17/24] target-ppc: Add POWER8's MMCR2/MMCRS SPRs, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 18/24] target-ppc: Add POWER8's FSCR SPR, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 14/24] target-ppc: Move POWER7/8 SPR registration to helpers,
Alexey Kardashevskiy <=
- [Qemu-ppc] [PATCH v3 07/24] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 12/24] target-ppc: Enable Hypervisor State bit in MSR for POWER5+, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 05/24] target-ppc: Add "POWER" prefix to MMCRA PMU registers, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 20/24] target-ppc: Add more POWER8's branch control SPRs, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 16/24] target-ppc: Add POWER7's TIR SPR, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 22/24] KVM: target-ppc: Enable transactional state migration, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 21/24] target-ppc: Enable PPR and VRSAVE SPRs migration, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 23/24] spapr_hcall: Split h_set_mode(), Alexey Kardashevskiy, 2014/05/27