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[Qemu-ppc] [PATCH v3 18/24] target-ppc: Add POWER8's FSCR SPR
From: |
Alexey Kardashevskiy |
Subject: |
[Qemu-ppc] [PATCH v3 18/24] target-ppc: Add POWER8's FSCR SPR |
Date: |
Tue, 27 May 2014 20:37:30 +1000 |
This adds an FSCR (Facility Status and Control Register) SPR.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index d0238e6..c2a84fd 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1272,6 +1272,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_CTRL (0x098)
#define SPR_MPC_CMPE (0x098)
#define SPR_MPC_CMPF (0x099)
+#define SPR_FSCR (0x099)
#define SPR_MPC_CMPG (0x09A)
#define SPR_MPC_CMPH (0x09B)
#define SPR_MPC_LCTRL1 (0x09C)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6bcb41c..0682739 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7598,6 +7598,14 @@ static void gen_spr_power8_branch_control(CPUPPCState
*env)
0x00000000);
}
+static void gen_spr_power8_common(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_FSCR, "FSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_FSCR, 0x00000000);
+}
+
static void init_proc_POWER(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -7640,6 +7648,7 @@ static void init_proc_POWER(CPUPPCState *env, int version)
if (version >= BOOK3S_CPU_POWER8) {
gen_spr_power8_branch_control(env);
gen_spr_power8_pmu(env);
+ gen_spr_power8_common(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {
--
1.8.4.rc4
- [Qemu-ppc] [PATCH v3 04/24] target-ppc: Copy and split gen_spr_7xx() for 970, (continued)
- [Qemu-ppc] [PATCH v3 04/24] target-ppc: Copy and split gen_spr_7xx() for 970, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 01/24] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 09/24] target-ppc: Add HID4 SPR for PPC970, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 11/24] target-ppc: Remove check_pow_970FX, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 13/24] target-ppc: Enable PMU SPRs migration, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 15/24] target-ppc: Refactor class init for POWER7/8, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 19/24] target-ppc: Add POWER8's TM SPRs, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 17/24] target-ppc: Add POWER8's MMCR2/MMCRS SPRs, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 18/24] target-ppc: Add POWER8's FSCR SPR,
Alexey Kardashevskiy <=
- [Qemu-ppc] [PATCH v3 14/24] target-ppc: Move POWER7/8 SPR registration to helpers, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 07/24] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 12/24] target-ppc: Enable Hypervisor State bit in MSR for POWER5+, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 05/24] target-ppc: Add "POWER" prefix to MMCRA PMU registers, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 20/24] target-ppc: Add more POWER8's branch control SPRs, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 16/24] target-ppc: Add POWER7's TIR SPR, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 22/24] KVM: target-ppc: Enable transactional state migration, Alexey Kardashevskiy, 2014/05/27