[Qemu-ppc] [PATCH v3 12/24] target-ppc: Enable Hypervisor State bit in MSR for POWER5+

[Alexey Kardashevskiy]

PowerISA 2.03 defines the HV bit. Since POWER5+ is 2.03-compliant,
enable the bit in msr_mask.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
 target-ppc/translate_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 703ad16..21916dd 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7606,6 +7606,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
                        PPC_64B |
                        PPC_SEGMENT_64B | PPC_SLBI;
     pcc->msr_mask = (1ull << MSR_SF) |
+                    (1ull << MSR_SHV) |
                     (1ull << MSR_VR) |
                     (1ull << MSR_POW) |
                     (1ull << MSR_EE) |
-- 
1.8.4.rc4