Re: [Qemu-ppc] [PATCH v3 16/24] target-ppc: Add POWER7's TIR SPR

[Alexander Graf]

On 27.05.14 12:37, Alexey Kardashevskiy wrote:
> This adds TIR (Thread Identification Register) SPR first defined in
> PowerISA 2.05.
>
> Signed-off-by: Alexey Kardashevskiy <address@hidden>
> ---
>   target-ppc/cpu.h            | 1 +
>   target-ppc/translate_init.c | 5 +++++
>   2 files changed, 6 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 6f2baef..14cbf8e 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1374,6 +1374,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>   #define SPR_BOOKE_GIVOR8      (0x1BB)
>   #define SPR_BOOKE_GIVOR13     (0x1BC)
>   #define SPR_BOOKE_GIVOR14     (0x1BD)
> +#define SPR_TIR               (0x1BE)
>   #define SPR_BOOKE_SPEFSCR     (0x200)
>   #define SPR_Exxx_BBEAR        (0x201)
>   #define SPR_Exxx_BBTAR        (0x202)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index e39a44d..83ef256 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7508,6 +7508,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
>                    SPR_NOACCESS, SPR_NOACCESS,
>                    &spr_read_generic, &spr_write_pir,
>                    0x00000000);
> +
> +    spr_register(env, SPR_TIR, "TIR",
> +                 &spr_read_generic, SPR_NOACCESS,
> +                 &spr_read_generic, SPR_NOACCESS,

According to the ISA (and I can confirm that real hardware thinks the 
same) TIR is supervisor privileged.


Alex