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[Qemu-ppc] [PATCH v3 21/24] target-ppc: Enable PPR and VRSAVE SPRs migra
From: |
Alexey Kardashevskiy |
Subject: |
[Qemu-ppc] [PATCH v3 21/24] target-ppc: Enable PPR and VRSAVE SPRs migration |
Date: |
Tue, 27 May 2014 20:37:33 +1000 |
This hooks SPR with theit "KVM set_one_reg" counterparts which enables
their migration.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
target-ppc/translate_init.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f0be5b1..39cc930 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7359,10 +7359,10 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
return;
}
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_VRSAVE, 0x00000000);
/* Can't find information on what this should be on reset. This
* value is the one used by 74xx processors. */
@@ -7597,10 +7597,10 @@ static void gen_spr_book3s_common(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x80800000);
- spr_register(env, SPR_PPR, "PPR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_PPR, "PPR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PPR, 0x00000000);
}
static void gen_spr_book3s_pcr(CPUPPCState *env)
--
1.8.4.rc4
- Re: [Qemu-ppc] [PATCH v3 18/24] target-ppc: Add POWER8's FSCR SPR, (continued)
- [Qemu-ppc] [PATCH v3 14/24] target-ppc: Move POWER7/8 SPR registration to helpers, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 07/24] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 12/24] target-ppc: Enable Hypervisor State bit in MSR for POWER5+, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 05/24] target-ppc: Add "POWER" prefix to MMCRA PMU registers, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 20/24] target-ppc: Add more POWER8's branch control SPRs, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 16/24] target-ppc: Add POWER7's TIR SPR, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 22/24] KVM: target-ppc: Enable transactional state migration, Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 21/24] target-ppc: Enable PPR and VRSAVE SPRs migration,
Alexey Kardashevskiy <=
- [Qemu-ppc] [PATCH v3 23/24] spapr_hcall: Split h_set_mode(), Alexey Kardashevskiy, 2014/05/27
- [Qemu-ppc] [PATCH v3 24/24] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE, Alexey Kardashevskiy, 2014/05/27
- Re: [Qemu-ppc] [PATCH v3 00/24] book3s powerpc classes rework, Alexander Graf, 2014/05/27
- Re: [Qemu-ppc] [PATCH v3 00/24] book3s powerpc classes rework, Alexey Kardashevskiy, 2014/05/28