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[PULL 21/41] target/arm: Implement v8.1M NOCP handling
From: |
Peter Maydell |
Subject: |
[PULL 21/41] target/arm: Implement v8.1M NOCP handling |
Date: |
Tue, 20 Oct 2020 16:56:36 +0100 |
>From v8.1M, disabled-coprocessor handling changes slightly:
* coprocessors 8, 9, 14 and 15 are also governed by the
cp10 enable bit, like cp11
* an extra range of instruction patterns is considered
to be inside the coprocessor space
We previously marked these up with TODO comments; implement the
correct behaviour.
Unfortunately there is no ID register field which indicates this
behaviour. We could in theory test an unrelated ID register which
indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch
>= 3 (low-overhead-loops), but it seems better to simply define a new
ARM_FEATURE_V8_1M feature flag and use it for this and other
new-in-v8.1M behaviour that isn't identifiable from the ID registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-3-peter.maydell@linaro.org
---
target/arm/cpu.h | 1 +
target/arm/m-nocp.decode | 10 ++++++----
target/arm/translate-vfp.c.inc | 17 +++++++++++++++--
3 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cfff1b5c8fe..74392fa0295 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1985,6 +1985,7 @@ enum arm_features {
ARM_FEATURE_VBAR, /* has cp15 VBAR */
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
+ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
};
static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
index 7182d7d1217..28c8ac6b94c 100644
--- a/target/arm/m-nocp.decode
+++ b/target/arm/m-nocp.decode
@@ -29,14 +29,16 @@
# If the coprocessor is not present or disabled then we will generate
# the NOCP exception; otherwise we let the insn through to the main decode.
+&nocp cp
+
{
# Special cases which do not take an early NOCP: VLLDM and VLSTM
VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
# TODO: VSCCLRM (new in v8.1M) is similar:
#VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0
- NOCP 111- 1110 ---- ---- ---- cp:4 ---- ----
- NOCP 111- 110- ---- ---- ---- cp:4 ---- ----
- # TODO: From v8.1M onwards we will also want this range to NOCP
- #NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- cp=10
+ NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp
+ NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
+ # From v8.1M onwards this range will also NOCP:
+ NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- &nocp cp=10
}
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 9b11b81f80d..a7ed9bc81b9 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -3459,7 +3459,7 @@ static bool trans_VLLDM_VLSTM(DisasContext *s,
arg_VLLDM_VLSTM *a)
return true;
}
-static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
+static bool trans_NOCP(DisasContext *s, arg_nocp *a)
{
/*
* Handle M-profile early check for disabled coprocessor:
@@ -3472,7 +3472,11 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
if (a->cp == 11) {
a->cp = 10;
}
- /* TODO: in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
+ if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
+ (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
+ /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
+ a->cp = 10;
+ }
if (a->cp != 10) {
gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
@@ -3489,6 +3493,15 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
return false;
}
+static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
+{
+ /* This range needs a coprocessor check for v8.1M and later only */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+ return false;
+ }
+ return trans_NOCP(s, a);
+}
+
static bool trans_VINS(DisasContext *s, arg_VINS *a)
{
TCGv_i32 rd, rm;
--
2.20.1
- [PULL 12/41] loads-stores.rst: add footnote that clarifies GETPC usage, (continued)
- [PULL 12/41] loads-stores.rst: add footnote that clarifies GETPC usage, Peter Maydell, 2020/10/20
- [PULL 13/41] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers, Peter Maydell, 2020/10/20
- [PULL 11/41] tests/qtest: Add npcm7xx timer test, Peter Maydell, 2020/10/20
- [PULL 14/41] hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers, Peter Maydell, 2020/10/20
- [PULL 15/41] target/arm: Remove redundant mmu_idx lookup, Peter Maydell, 2020/10/20
- [PULL 16/41] target/arm: Fix reported EL for mte_check_fail, Peter Maydell, 2020/10/20
- [PULL 17/41] target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11, Peter Maydell, 2020/10/20
- [PULL 18/41] microbit_i2c: Fix coredump when dump-vmstate, Peter Maydell, 2020/10/20
- [PULL 19/41] hw/arm/nseries: Fix loading kernel image on n8x0 machines, Peter Maydell, 2020/10/20
- [PULL 20/41] decodetree: Fix codegen for non-overlapping group inside overlapping group, Peter Maydell, 2020/10/20
- [PULL 21/41] target/arm: Implement v8.1M NOCP handling,
Peter Maydell <=
- [PULL 22/41] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/20
- [PULL 23/41] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/20
- [PULL 24/41] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/20
- [PULL 25/41] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/20
- [PULL 26/41] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/20
- [PULL 27/41] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/20
- [PULL 28/41] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16, Peter Maydell, 2020/10/20
- [PULL 31/41] linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI, Peter Maydell, 2020/10/20
- [PULL 29/41] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, Peter Maydell, 2020/10/20
- [PULL 30/41] linux-user/aarch64: Reset btype for signals, Peter Maydell, 2020/10/20