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[PULL 25/41] target/arm: Implement v8.1M branch-future insns (as NOPs)
From: |
Peter Maydell |
Subject: |
[PULL 25/41] target/arm: Implement v8.1M branch-future insns (as NOPs) |
Date: |
Tue, 20 Oct 2020 16:56:40 +0100 |
v8.1M implements a new 'branch future' feature, which is a
set of instructions that request the CPU to perform a branch
"in the future", when it reaches a particular execution address.
In hardware, the expected implementation is that the information
about the branch location and destination is cached and then
acted upon when execution reaches the specified address.
However the architecture permits an implementation to discard
this cached information at any point, and so guest code must
always include a normal branch insn at the branch point as
a fallback. In particular, an implementation is specifically
permitted to treat all BF insns as NOPs (which is equivalent
to discarding the cached information immediately).
For QEMU, implementing this caching of branch information
would be complicated and would not improve the speed of
execution at all, so we make the IMPDEF choice to implement
all BF insns as NOPs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-7-peter.maydell@linaro.org
---
target/arm/cpu.h | 6 ++++++
target/arm/t32.decode | 13 ++++++++++++-
target/arm/translate.c | 20 ++++++++++++++++++++
3 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 74392fa0295..a432f301f11 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3473,6 +3473,12 @@ static inline bool isar_feature_aa32_arm_div(const
ARMISARegisters *id)
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
}
+static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
+{
+ /* (M-profile) low-overhead loops and branch future */
+ return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
+}
+
static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 7d5e000e82c..3015731a8d0 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -648,4 +648,15 @@ MRC 1110 1110 ... 1 .... .... .... ... 1 ....
@mcr
B 1111 0. .......... 10.1 ............ @branch24
BL 1111 0. .......... 11.1 ............ @branch24
-BLX_i 1111 0. .......... 11.0 ............ @branch24
+{
+ # BLX_i is non-M-profile only
+ BLX_i 1111 0. .......... 11.0 ............ @branch24
+ # M-profile only: loop and branch insns
+ [
+ # All these BF insns have boff != 0b0000; we NOP them all
+ BF 1111 0 boff:4 ------- 1100 - ---------- 1 # BFL
+ BF 1111 0 boff:4 0 ------ 1110 - ---------- 1 # BFCSEL
+ BF 1111 0 boff:4 10 ----- 1110 - ---------- 1 # BF
+ BF 1111 0 boff:4 11 ----- 1110 0 0000000000 1 # BFX, BFLX
+ ]
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index dc3a4031db7..a5ebe568804 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7971,6 +7971,26 @@ static bool trans_BLX_suffix(DisasContext *s,
arg_BLX_suffix *a)
return true;
}
+static bool trans_BF(DisasContext *s, arg_BF *a)
+{
+ /*
+ * M-profile branch future insns. The architecture permits an
+ * implementation to implement these as NOPs (equivalent to
+ * discarding the LO_BRANCH_INFO cache immediately), and we
+ * take that IMPDEF option because for QEMU a "real" implementation
+ * would be complicated and wouldn't execute any faster.
+ */
+ if (!dc_isar_feature(aa32_lob, s)) {
+ return false;
+ }
+ if (a->boff == 0) {
+ /* SEE "Related encodings" (loop insns) */
+ return false;
+ }
+ /* Handle as NOP */
+ return true;
+}
+
static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
{
TCGv_i32 addr, tmp;
--
2.20.1
- [PULL 15/41] target/arm: Remove redundant mmu_idx lookup, (continued)
- [PULL 15/41] target/arm: Remove redundant mmu_idx lookup, Peter Maydell, 2020/10/20
- [PULL 16/41] target/arm: Fix reported EL for mte_check_fail, Peter Maydell, 2020/10/20
- [PULL 17/41] target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11, Peter Maydell, 2020/10/20
- [PULL 18/41] microbit_i2c: Fix coredump when dump-vmstate, Peter Maydell, 2020/10/20
- [PULL 19/41] hw/arm/nseries: Fix loading kernel image on n8x0 machines, Peter Maydell, 2020/10/20
- [PULL 20/41] decodetree: Fix codegen for non-overlapping group inside overlapping group, Peter Maydell, 2020/10/20
- [PULL 21/41] target/arm: Implement v8.1M NOCP handling, Peter Maydell, 2020/10/20
- [PULL 22/41] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/20
- [PULL 23/41] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/20
- [PULL 24/41] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/20
- [PULL 25/41] target/arm: Implement v8.1M branch-future insns (as NOPs),
Peter Maydell <=
- [PULL 26/41] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/20
- [PULL 27/41] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/20
- [PULL 28/41] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16, Peter Maydell, 2020/10/20
- [PULL 31/41] linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI, Peter Maydell, 2020/10/20
- [PULL 29/41] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, Peter Maydell, 2020/10/20
- [PULL 30/41] linux-user/aarch64: Reset btype for signals, Peter Maydell, 2020/10/20
- [PULL 32/41] include/elf: Add defines related to GNU property notes for AArch64, Peter Maydell, 2020/10/20
- [PULL 33/41] linux-user/elfload: Avoid leaking interp_name using GLib memory API, Peter Maydell, 2020/10/20
- [PULL 35/41] linux-user/elfload: Adjust iteration over phdr, Peter Maydell, 2020/10/20
- [PULL 36/41] linux-user/elfload: Move PT_INTERP detection to first loop, Peter Maydell, 2020/10/20