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[PULL 16/41] target/arm: Fix reported EL for mte_check_fail
From: |
Peter Maydell |
Subject: |
[PULL 16/41] target/arm: Fix reported EL for mte_check_fail |
Date: |
Tue, 20 Oct 2020 16:56:31 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
The reporting in AArch64.TagCheckFail only depends on PSTATE.EL,
and not the AccType of the operation. There are two guest
visible problems that affect LDTR and STTR because of this:
(1) Selecting TCF0 vs TCF1 to decide on reporting,
(2) Report "data abort same el" not "data abort lower el".
Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-id: 20201008162155.161886-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/mte_helper.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 734cc5ca675..153bd1e9df8 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -525,14 +525,10 @@ static void mte_check_fail(CPUARMState *env, uint32_t
desc,
reg_el = regime_el(env, arm_mmu_idx);
sctlr = env->cp15.sctlr_el[reg_el];
- switch (arm_mmu_idx) {
- case ARMMMUIdx_E10_0:
- case ARMMMUIdx_E20_0:
- el = 0;
+ el = arm_current_el(env);
+ if (el == 0) {
tcf = extract64(sctlr, 38, 2);
- break;
- default:
- el = reg_el;
+ } else {
tcf = extract64(sctlr, 40, 2);
}
--
2.20.1
- [PULL 06/41] hw/timer/bcm2835: Rename variable holding CTRL_STATUS register, (continued)
- [PULL 06/41] hw/timer/bcm2835: Rename variable holding CTRL_STATUS register, Peter Maydell, 2020/10/20
- [PULL 08/41] hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs, Peter Maydell, 2020/10/20
- [PULL 07/41] hw/timer/bcm2835: Support the timer COMPARE registers, Peter Maydell, 2020/10/20
- [PULL 09/41] accel/tcg: Add tlb_flush_page_bits_by_mmuidx*, Peter Maydell, 2020/10/20
- [PULL 10/41] target/arm: Use tlb_flush_page_bits_by_mmuidx*, Peter Maydell, 2020/10/20
- [PULL 12/41] loads-stores.rst: add footnote that clarifies GETPC usage, Peter Maydell, 2020/10/20
- [PULL 13/41] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers, Peter Maydell, 2020/10/20
- [PULL 11/41] tests/qtest: Add npcm7xx timer test, Peter Maydell, 2020/10/20
- [PULL 14/41] hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers, Peter Maydell, 2020/10/20
- [PULL 15/41] target/arm: Remove redundant mmu_idx lookup, Peter Maydell, 2020/10/20
- [PULL 16/41] target/arm: Fix reported EL for mte_check_fail,
Peter Maydell <=
- [PULL 17/41] target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11, Peter Maydell, 2020/10/20
- [PULL 18/41] microbit_i2c: Fix coredump when dump-vmstate, Peter Maydell, 2020/10/20
- [PULL 19/41] hw/arm/nseries: Fix loading kernel image on n8x0 machines, Peter Maydell, 2020/10/20
- [PULL 20/41] decodetree: Fix codegen for non-overlapping group inside overlapping group, Peter Maydell, 2020/10/20
- [PULL 21/41] target/arm: Implement v8.1M NOCP handling, Peter Maydell, 2020/10/20
- [PULL 22/41] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/20
- [PULL 23/41] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/20
- [PULL 24/41] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/20
- [PULL 25/41] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/20
- [PULL 26/41] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/20