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[PULL 10/41] target/arm: Use tlb_flush_page_bits_by_mmuidx*
From: |
Peter Maydell |
Subject: |
[PULL 10/41] target/arm: Use tlb_flush_page_bits_by_mmuidx* |
Date: |
Tue, 20 Oct 2020 16:56:25 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
When TBI is enabled in a given regime, 56 bits of the address
are significant and we need to clear out any other matching
virtual addresses with differing tags.
The other uses of tlb_flush_page (without mmuidx) in this file
are only used by aarch32 mode.
Fixes: 38d931687fa1
Reported-by: Jordan Frank <jordanfrank@fb.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201016210754.818257-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 46 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 39 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index cd0779ff5fa..f49b045d366 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -50,6 +50,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong
address,
#endif
static void switch_mode(CPUARMState *env, int mode);
+static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
{
@@ -4457,6 +4458,33 @@ static int vae1_tlbmask(CPUARMState *env)
}
}
+/* Return 56 if TBI is enabled, 64 otherwise. */
+static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
+ uint64_t addr)
+{
+ uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
+ int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
+ int select = extract64(addr, 55, 1);
+
+ return (tbi >> select) & 1 ? 56 : 64;
+}
+
+static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
+{
+ ARMMMUIdx mmu_idx;
+
+ /* Only the regime of the mmu_idx below is significant. */
+ if (arm_is_secure_below_el3(env)) {
+ mmu_idx = ARMMMUIdx_SE10_0;
+ } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
+ == (HCR_E2H | HCR_TGE)) {
+ mmu_idx = ARMMMUIdx_E20_0;
+ } else {
+ mmu_idx = ARMMMUIdx_E10_0;
+ }
+ return tlbbits_for_regime(env, mmu_idx, addr);
+}
+
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4593,8 +4621,9 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env);
int mask = vae1_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
+ int bits = vae1_tlbbits(env, pageaddr);
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
}
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4608,11 +4637,12 @@ static void tlbi_aa64_vae1_write(CPUARMState *env,
const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env);
int mask = vae1_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
+ int bits = vae1_tlbbits(env, pageaddr);
if (tlb_force_broadcast(env)) {
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask,
bits);
} else {
- tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
+ tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
}
}
@@ -4621,9 +4651,10 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
{
CPUState *cs = env_cpu(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
+ int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr);
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_E2);
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
+ ARMMMUIdxBit_E2, bits);
}
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4631,9 +4662,10 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
{
CPUState *cs = env_cpu(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
+ int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_SE3);
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
+ ARMMMUIdxBit_SE3, bits);
}
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
- [PULL 00/41] target-arm queue, Peter Maydell, 2020/10/20
- [PULL 01/41] target/arm: Fix SMLAD incorrect setting of Q bit, Peter Maydell, 2020/10/20
- [PULL 02/41] target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest, Peter Maydell, 2020/10/20
- [PULL 03/41] hw/arm/strongarm: Fix 'time to transmit a char' unit comment, Peter Maydell, 2020/10/20
- [PULL 04/41] hw/arm: Restrict APEI tables generation to the 'virt' machine, Peter Maydell, 2020/10/20
- [PULL 05/41] hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition, Peter Maydell, 2020/10/20
- [PULL 06/41] hw/timer/bcm2835: Rename variable holding CTRL_STATUS register, Peter Maydell, 2020/10/20
- [PULL 08/41] hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs, Peter Maydell, 2020/10/20
- [PULL 07/41] hw/timer/bcm2835: Support the timer COMPARE registers, Peter Maydell, 2020/10/20
- [PULL 09/41] accel/tcg: Add tlb_flush_page_bits_by_mmuidx*, Peter Maydell, 2020/10/20
- [PULL 10/41] target/arm: Use tlb_flush_page_bits_by_mmuidx*,
Peter Maydell <=
- [PULL 12/41] loads-stores.rst: add footnote that clarifies GETPC usage, Peter Maydell, 2020/10/20
- [PULL 13/41] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers, Peter Maydell, 2020/10/20
- [PULL 11/41] tests/qtest: Add npcm7xx timer test, Peter Maydell, 2020/10/20
- [PULL 14/41] hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers, Peter Maydell, 2020/10/20
- [PULL 15/41] target/arm: Remove redundant mmu_idx lookup, Peter Maydell, 2020/10/20
- [PULL 16/41] target/arm: Fix reported EL for mte_check_fail, Peter Maydell, 2020/10/20
- [PULL 17/41] target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11, Peter Maydell, 2020/10/20
- [PULL 18/41] microbit_i2c: Fix coredump when dump-vmstate, Peter Maydell, 2020/10/20
- [PULL 19/41] hw/arm/nseries: Fix loading kernel image on n8x0 machines, Peter Maydell, 2020/10/20
- [PULL 20/41] decodetree: Fix codegen for non-overlapping group inside overlapping group, Peter Maydell, 2020/10/20