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[PULL 13/41] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
From: |
Peter Maydell |
Subject: |
[PULL 13/41] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers |
Date: |
Tue, 20 Oct 2020 16:56:28 +0100 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Add trace events for GPU and CPU IRQs.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201017180731.1165871-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/bcm2835_ic.c | 4 +++-
hw/intc/trace-events | 4 ++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c
index 53ab8f58810..9000d995e81 100644
--- a/hw/intc/bcm2835_ic.c
+++ b/hw/intc/bcm2835_ic.c
@@ -18,6 +18,7 @@
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "trace.h"
#define GPU_IRQS 64
#define ARM_IRQS 8
@@ -51,7 +52,6 @@ static void bcm2835_ic_update(BCM2835ICState *s)
set = (s->gpu_irq_level & s->gpu_irq_enable)
|| (s->arm_irq_level & s->arm_irq_enable);
qemu_set_irq(s->irq, set);
-
}
static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
@@ -59,6 +59,7 @@ static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int
level)
BCM2835ICState *s = opaque;
assert(irq >= 0 && irq < 64);
+ trace_bcm2835_ic_set_gpu_irq(irq, level);
s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);
bcm2835_ic_update(s);
}
@@ -68,6 +69,7 @@ static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int
level)
BCM2835ICState *s = opaque;
assert(irq >= 0 && irq < 8);
+ trace_bcm2835_ic_set_cpu_irq(irq, level);
s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);
bcm2835_ic_update(s);
}
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 527c3f76cae..22782b3f089 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -199,3 +199,7 @@ nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned
size) "NVIC sysreg wri
heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u:
0x%"PRIx64
heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u:
0x%"PRIx64
heathrow_set_irq(int num, int level) "set_irq: num=0x%02x level=%d"
+
+# bcm2835_ic.c
+bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d level %d"
+bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d"
--
2.20.1
- [PULL 02/41] target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest, (continued)
- [PULL 02/41] target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest, Peter Maydell, 2020/10/20
- [PULL 03/41] hw/arm/strongarm: Fix 'time to transmit a char' unit comment, Peter Maydell, 2020/10/20
- [PULL 04/41] hw/arm: Restrict APEI tables generation to the 'virt' machine, Peter Maydell, 2020/10/20
- [PULL 05/41] hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition, Peter Maydell, 2020/10/20
- [PULL 06/41] hw/timer/bcm2835: Rename variable holding CTRL_STATUS register, Peter Maydell, 2020/10/20
- [PULL 08/41] hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs, Peter Maydell, 2020/10/20
- [PULL 07/41] hw/timer/bcm2835: Support the timer COMPARE registers, Peter Maydell, 2020/10/20
- [PULL 09/41] accel/tcg: Add tlb_flush_page_bits_by_mmuidx*, Peter Maydell, 2020/10/20
- [PULL 10/41] target/arm: Use tlb_flush_page_bits_by_mmuidx*, Peter Maydell, 2020/10/20
- [PULL 12/41] loads-stores.rst: add footnote that clarifies GETPC usage, Peter Maydell, 2020/10/20
- [PULL 13/41] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers,
Peter Maydell <=
- [PULL 11/41] tests/qtest: Add npcm7xx timer test, Peter Maydell, 2020/10/20
- [PULL 14/41] hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers, Peter Maydell, 2020/10/20
- [PULL 15/41] target/arm: Remove redundant mmu_idx lookup, Peter Maydell, 2020/10/20
- [PULL 16/41] target/arm: Fix reported EL for mte_check_fail, Peter Maydell, 2020/10/20
- [PULL 17/41] target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11, Peter Maydell, 2020/10/20
- [PULL 18/41] microbit_i2c: Fix coredump when dump-vmstate, Peter Maydell, 2020/10/20
- [PULL 19/41] hw/arm/nseries: Fix loading kernel image on n8x0 machines, Peter Maydell, 2020/10/20
- [PULL 20/41] decodetree: Fix codegen for non-overlapping group inside overlapping group, Peter Maydell, 2020/10/20
- [PULL 21/41] target/arm: Implement v8.1M NOCP handling, Peter Maydell, 2020/10/20
- [PULL 22/41] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/20