[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 28/41] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP1
From: |
Peter Maydell |
Subject: |
[PULL 28/41] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16 |
Date: |
Tue, 20 Oct 2020 16:56:43 +0100 |
M-profile CPUs with half-precision floating point support should
be able to write to FPSCR.FZ16, but an M-profile specific masking
of the value at the top of vfp_set_fpscr() currently prevents that.
This is not yet an active bug because we have no M-profile
FP16 CPUs, but needs to be fixed before we can add any.
The bits that the masking is effectively preventing from being
set are the A-profile only short-vector Len and Stride fields,
plus the Neon QC bit. Rearrange the order of the function so
that those fields are handled earlier and only under a suitable
guard; this allows us to drop the M-profile specific masking,
making FZ16 writeable.
This change also makes the QC bit correctly RAZ/WI for older
no-Neon A-profile cores.
This refactoring also paves the way for the low-overhead-branch
LTPSIZE field, which uses some of the bits that are used for
A-profile Stride and Len.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-10-peter.maydell@linaro.org
---
target/arm/vfp_helper.c | 47 ++++++++++++++++++++++++-----------------
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index abfdb6a8e23..364856498c4 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -194,36 +194,45 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
val &= ~FPCR_FZ16;
}
- if (arm_feature(env, ARM_FEATURE_M)) {
+ vfp_set_fpscr_to_host(env, val);
+
+ if (!arm_feature(env, ARM_FEATURE_M)) {
/*
- * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
- * and also for the trapped-exception-handling bits IxE.
+ * Short-vector length and stride; on M-profile these bits
+ * are used for different purposes.
+ * We can't make this conditional be "if MVFR0.FPShVec != 0",
+ * because in v7A no-short-vector-support cores still had to
+ * allow Stride/Len to be written with the only effect that
+ * some insns are required to UNDEF if the guest sets them.
+ *
+ * TODO: if M-profile MVE implemented, set LTPSIZE.
*/
- val &= 0xf7c0009f;
+ env->vfp.vec_len = extract32(val, 16, 3);
+ env->vfp.vec_stride = extract32(val, 20, 2);
}
- vfp_set_fpscr_to_host(env, val);
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
+ /*
+ * The bit we set within fpscr_q is arbitrary; the register as a
+ * whole being zero/non-zero is what counts.
+ * TODO: M-profile MVE also has a QC bit.
+ */
+ env->vfp.qc[0] = val & FPCR_QC;
+ env->vfp.qc[1] = 0;
+ env->vfp.qc[2] = 0;
+ env->vfp.qc[3] = 0;
+ }
/*
* We don't implement trapped exception handling, so the
* trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
*
- * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
- * (which are stored in fp_status), and the other RES0 bits
- * in between, then we clear all of the low 16 bits.
+ * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
+ * fp_status; QC, Len and Stride are stored separately earlier.
+ * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
+ * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
*/
env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
- env->vfp.vec_len = (val >> 16) & 7;
- env->vfp.vec_stride = (val >> 20) & 3;
-
- /*
- * The bit we set within fpscr_q is arbitrary; the register as a
- * whole being zero/non-zero is what counts.
- */
- env->vfp.qc[0] = val & FPCR_QC;
- env->vfp.qc[1] = 0;
- env->vfp.qc[2] = 0;
- env->vfp.qc[3] = 0;
}
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
--
2.20.1
- [PULL 18/41] microbit_i2c: Fix coredump when dump-vmstate, (continued)
- [PULL 18/41] microbit_i2c: Fix coredump when dump-vmstate, Peter Maydell, 2020/10/20
- [PULL 19/41] hw/arm/nseries: Fix loading kernel image on n8x0 machines, Peter Maydell, 2020/10/20
- [PULL 20/41] decodetree: Fix codegen for non-overlapping group inside overlapping group, Peter Maydell, 2020/10/20
- [PULL 21/41] target/arm: Implement v8.1M NOCP handling, Peter Maydell, 2020/10/20
- [PULL 22/41] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/20
- [PULL 23/41] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/20
- [PULL 24/41] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/20
- [PULL 25/41] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/20
- [PULL 26/41] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/20
- [PULL 27/41] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/20
- [PULL 28/41] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16,
Peter Maydell <=
- [PULL 31/41] linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI, Peter Maydell, 2020/10/20
- [PULL 29/41] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, Peter Maydell, 2020/10/20
- [PULL 30/41] linux-user/aarch64: Reset btype for signals, Peter Maydell, 2020/10/20
- [PULL 32/41] include/elf: Add defines related to GNU property notes for AArch64, Peter Maydell, 2020/10/20
- [PULL 33/41] linux-user/elfload: Avoid leaking interp_name using GLib memory API, Peter Maydell, 2020/10/20
- [PULL 35/41] linux-user/elfload: Adjust iteration over phdr, Peter Maydell, 2020/10/20
- [PULL 36/41] linux-user/elfload: Move PT_INTERP detection to first loop, Peter Maydell, 2020/10/20
- [PULL 38/41] linux-user/elfload: Use Error for load_elf_interp, Peter Maydell, 2020/10/20
- [PULL 34/41] linux-user/elfload: Fix coding style in load_elf_image, Peter Maydell, 2020/10/20
- [PULL 37/41] linux-user/elfload: Use Error for load_elf_image, Peter Maydell, 2020/10/20