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[Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 regi
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2 |
Date: |
Wed, 28 Aug 2019 18:26:27 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 2.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 7 ++++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 597afa8..eebdc9f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -294,6 +294,13 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
+#define CP0_REG02__TCSTATUS 1
+#define CP0_REG02__TCBIND 2
+#define CP0_REG02__TCRESTART 3
+#define CP0_REG02__TCHALT 4
+#define CP0_REG02__TCCONTEXT 5
+#define CP0_REG02__TCSCHEDULE 6
+#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e350545..6e65312 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6929,7 +6929,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6946,37 +6946,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
}
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -7698,41 +7698,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
@@ -8449,41 +8449,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -9170,41 +9170,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_dmtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
--
2.7.4
- [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 04/30] target/mips: Clean up handling of CP0 register 3, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 01/30] target/mips: Clean up handling of CP0 register 0, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 02/30] target/mips: Clean up handling of CP0 register 1, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 20/30] target/mips: Clean up handling of CP0 register 19, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 15/30] target/mips: Clean up handling of CP0 register 14, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 08/30] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/28