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[Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 regi
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17 |
Date: |
Wed, 28 Aug 2019 18:26:42 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 17.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a3df2a5..6842531 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6671,12 +6671,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
ctx->CP0_LLAddr_shift);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfhc0_maar(arg, cpu_env);
register_name = "MAAR";
@@ -6772,7 +6772,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
/*
* LLAddr is read-only (the only exception is bit 0 if LLB is
* supported); the CP0_LLAddr_rw_bitmask does not seem to be
@@ -6781,7 +6781,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
*/
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mthc0_maar(cpu_env, arg);
register_name = "MAAR";
@@ -7333,16 +7333,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -8073,16 +8073,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
@@ -8819,16 +8819,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_dmfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_dmfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -9541,16 +9541,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
--
2.7.4
- [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8, (continued)
- [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 20/30] target/mips: Clean up handling of CP0 register 19, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 15/30] target/mips: Clean up handling of CP0 register 14, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 08/30] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 17/30] target/mips: Clean up handling of CP0 register 16, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 11/30] target/mips: Clean up handling of CP0 register 10, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 23/30] target/mips: Clean up handling of CP0 register 24, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 19/30] target/mips: Clean up handling of CP0 register 18, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 21/30] target/mips: Clean up handling of CP0 register 20, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 22/30] target/mips: Clean up handling of CP0 register 23, Aleksandar Markovic, 2019/08/28