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[Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 regi
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15 |
Date: |
Wed, 28 Aug 2019 18:26:40 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 15.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 8e6376a..f709a92 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -369,6 +369,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE 2
#define CP0_REG15__CMGCRBASE 3
+#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7644dda..a0a2d43 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7271,17 +7271,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -8009,11 +8009,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -8759,16 +8759,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -9486,11 +9486,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
--
2.7.4
- [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6, (continued)
- [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v2 20/30] target/mips: Clean up handling of CP0 register 19, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 15/30] target/mips: Clean up handling of CP0 register 14, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 08/30] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 17/30] target/mips: Clean up handling of CP0 register 16, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 11/30] target/mips: Clean up handling of CP0 register 10, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 23/30] target/mips: Clean up handling of CP0 register 24, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 19/30] target/mips: Clean up handling of CP0 register 18, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 21/30] target/mips: Clean up handling of CP0 register 20, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 22/30] target/mips: Clean up handling of CP0 register 23, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 27/30] target/mips: Clean up handling of CP0 register 28, Aleksandar Markovic, 2019/08/28