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[Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 regi
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6 |
Date: |
Wed, 28 Aug 2019 18:26:31 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 6.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 6 ++++++
target/mips/translate.c | 56 ++++++++++++++++++++++++-------------------------
2 files changed, 34 insertions(+), 28 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 248f7df..74a760e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -323,6 +323,12 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
+#define CP0_REG06__SRSCONF0 1
+#define CP0_REG06__SRSCONF1 2
+#define CP0_REG06__SRSCONF2 3
+#define CP0_REG06__SRSCONF3 4
+#define CP0_REG06__SRSCONF4 5
+#define CP0_REG06__PWCTL 6
/* CP0 Register 07 */
#define CP0_REG07__HWRENA 0
/* CP0 Register 08 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4395345..451805f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7091,36 +7091,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -7831,36 +7831,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
@@ -8582,36 +8582,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -9304,36 +9304,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
--
2.7.4
- [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 04/30] target/mips: Clean up handling of CP0 register 3, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 01/30] target/mips: Clean up handling of CP0 register 0, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 02/30] target/mips: Clean up handling of CP0 register 1, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17, Aleksandar Markovic, 2019/08/28
- [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15, Aleksandar Markovic, 2019/08/28