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[PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch
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From: |
Alistair Francis |
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Subject: |
[PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch |
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Date: |
Fri, 17 Jan 2025 15:55:49 +1000 |
From: Clément Léger <cleger@rivosinc.com>
Add the switch to enable the Smdbltrp ISA extension.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250110125441.3208676-10-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e3ed11b0fd..bddf1ba75e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind),
+ ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
@@ -1626,6 +1627,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
+ MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false),
MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
--
2.47.1
- [PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg, (continued)
- [PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg, Alistair Francis, 2025/01/17
- [PULL 37/50] target/riscv: Add implied rule for counter delegation extensions, Alistair Francis, 2025/01/17
- [PULL 34/50] target/riscv: Add select value range check for counter delegation, Alistair Francis, 2025/01/17
- [PULL 39/50] target/riscv: Fix henvcfg potentially containing stale bits, Alistair Francis, 2025/01/17
- [PULL 40/50] target/riscv: Add Ssdbltrp CSRs handling, Alistair Francis, 2025/01/17
- [PULL 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/17
- [PULL 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/17
- [PULL 32/50] target/riscv: Add properties for counter delegation ISA extensions, Alistair Francis, 2025/01/17
- [PULL 33/50] target/riscv: Add counter delegation definitions, Alistair Francis, 2025/01/17
- [PULL 36/50] target/riscv: Invoke pmu init after feature enable, Alistair Francis, 2025/01/17
- [PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch,
Alistair Francis <=
- [PULL 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache, Alistair Francis, 2025/01/17
- [PULL 46/50] target/riscv: Implement Smdbltrp behavior, Alistair Francis, 2025/01/17
- [PULL 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch, Alistair Francis, 2025/01/17
- [PULL 44/50] target/riscv: Add Smdbltrp CSRs handling, Alistair Francis, 2025/01/17
- [PULL 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events, Alistair Francis, 2025/01/17