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[PULL 37/50] target/riscv: Add implied rule for counter delegation exten
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From: |
Alistair Francis |
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Subject: |
[PULL 37/50] target/riscv: Add implied rule for counter delegation extensions |
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Date: |
Fri, 17 Jan 2025 15:55:39 +1000 |
From: Atish Patra <atishp@rivosinc.com>
The counter delegation/configuration extensions depend on the following
extensions.
1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSRs
Add an implied rule so that these extensions are enabled by default
if the sscfg extension is enabled.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-10-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index da40f68715..671fc3d1c1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2760,6 +2760,16 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
},
};
+static RISCVCPUImpliedExtsRule SSCFG_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_ssccfg),
+ .implied_multi_exts = {
+ CPU_CFG_OFFSET(ext_smcsrind), CPU_CFG_OFFSET(ext_sscsrind),
+ CPU_CFG_OFFSET(ext_smcdeleg),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
&RVM_IMPLIED, &RVV_IMPLIED, NULL
@@ -2777,7 +2787,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]
= {
&ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
&ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
&ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
- &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
+ &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,
NULL
};
--
2.47.1
- [PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi, (continued)
- [PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi, Alistair Francis, 2025/01/17
- [PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu, Alistair Francis, 2025/01/17
- [PULL 27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu, Alistair Francis, 2025/01/17
- [PULL 28/50] target/riscv: Add properties for Indirect CSR Access extension, Alistair Francis, 2025/01/17
- [PULL 31/50] target/riscv: Support generic CSR indirect access, Alistair Francis, 2025/01/17
- [PULL 35/50] target/riscv: Add counter delegation/configuration support, Alistair Francis, 2025/01/17
- [PULL 30/50] target/riscv: Enable S*stateen bits for AIA, Alistair Francis, 2025/01/17
- [PULL 42/50] target/riscv: Implement Ssdbltrp exception handling, Alistair Francis, 2025/01/17
- [PULL 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Alistair Francis, 2025/01/17
- [PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg, Alistair Francis, 2025/01/17
- [PULL 37/50] target/riscv: Add implied rule for counter delegation extensions,
Alistair Francis <=
- [PULL 34/50] target/riscv: Add select value range check for counter delegation, Alistair Francis, 2025/01/17
- [PULL 39/50] target/riscv: Fix henvcfg potentially containing stale bits, Alistair Francis, 2025/01/17
- [PULL 40/50] target/riscv: Add Ssdbltrp CSRs handling, Alistair Francis, 2025/01/17
- [PULL 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/17
- [PULL 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/17
- [PULL 32/50] target/riscv: Add properties for counter delegation ISA extensions, Alistair Francis, 2025/01/17
- [PULL 33/50] target/riscv: Add counter delegation definitions, Alistair Francis, 2025/01/17
- [PULL 36/50] target/riscv: Invoke pmu init after feature enable, Alistair Francis, 2025/01/17
- [PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch, Alistair Francis, 2025/01/17