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[PATCH v5 10/11] target/riscv: Add implied rule for counter delegation e
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From: |
Atish Patra |
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Subject: |
[PATCH v5 10/11] target/riscv: Add implied rule for counter delegation extensions |
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Date: |
Fri, 10 Jan 2025 00:21:38 -0800 |
The counter delegation/configuration extensions depend on the following
extensions.
1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSRs
Add an implied rule so that these extensions are enabled by default
if the sscfg extension is enabled.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index da40f6871572..671fc3d1c1fc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2760,6 +2760,16 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
},
};
+static RISCVCPUImpliedExtsRule SSCFG_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_ssccfg),
+ .implied_multi_exts = {
+ CPU_CFG_OFFSET(ext_smcsrind), CPU_CFG_OFFSET(ext_sscsrind),
+ CPU_CFG_OFFSET(ext_smcdeleg),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
&RVM_IMPLIED, &RVV_IMPLIED, NULL
@@ -2777,7 +2787,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]
= {
&ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
&ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
&ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
- &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
+ &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,
NULL
};
--
2.34.1
- [PATCH v5 00/11] Add RISC-V Counter delegation ISA extension support, Atish Patra, 2025/01/10
- [PATCH v5 01/11] target/riscv: Add properties for Indirect CSR Access extension, Atish Patra, 2025/01/10
- [PATCH v5 02/11] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2025/01/10
- [PATCH v5 03/11] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2025/01/10
- [PATCH v5 04/11] target/riscv: Support generic CSR indirect access, Atish Patra, 2025/01/10
- [PATCH v5 06/11] target/riscv: Add counter delegation definitions, Atish Patra, 2025/01/10
- [PATCH v5 05/11] target/riscv: Add properties for counter delegation ISA extensions, Atish Patra, 2025/01/10
- [PATCH v5 07/11] target/riscv: Add select value range check for counter delegation, Atish Patra, 2025/01/10
- [PATCH v5 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Atish Patra, 2025/01/10
- [PATCH v5 08/11] target/riscv: Add counter delegation/configuration support, Atish Patra, 2025/01/10
- [PATCH v5 10/11] target/riscv: Add implied rule for counter delegation extensions,
Atish Patra <=
- [PATCH v5 09/11] target/riscv: Invoke pmu init after feature enable, Atish Patra, 2025/01/10