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[PATCH v5 01/11] target/riscv: Add properties for Indirect CSR Access ex
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From: |
Atish Patra |
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Subject: |
[PATCH v5 01/11] target/riscv: Add properties for Indirect CSR Access extension |
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Date: |
Fri, 10 Jan 2025 00:21:29 -0800 |
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dace670e5e0f..4f5772ae5b60 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -192,6 +192,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
+ ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
@@ -201,6 +202,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind),
ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index ee7c90871047..4fe2144ec713 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -79,6 +79,8 @@ struct RISCVCPUConfig {
bool ext_smstateen;
bool ext_sstc;
bool ext_smcntrpmf;
+ bool ext_smcsrind;
+ bool ext_sscsrind;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
--
2.34.1
- [PATCH v5 00/11] Add RISC-V Counter delegation ISA extension support, Atish Patra, 2025/01/10
- [PATCH v5 01/11] target/riscv: Add properties for Indirect CSR Access extension,
Atish Patra <=
- [PATCH v5 02/11] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2025/01/10
- [PATCH v5 03/11] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2025/01/10
- [PATCH v5 04/11] target/riscv: Support generic CSR indirect access, Atish Patra, 2025/01/10
- [PATCH v5 06/11] target/riscv: Add counter delegation definitions, Atish Patra, 2025/01/10
- [PATCH v5 05/11] target/riscv: Add properties for counter delegation ISA extensions, Atish Patra, 2025/01/10
- [PATCH v5 07/11] target/riscv: Add select value range check for counter delegation, Atish Patra, 2025/01/10
- [PATCH v5 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Atish Patra, 2025/01/10
- [PATCH v5 08/11] target/riscv: Add counter delegation/configuration support, Atish Patra, 2025/01/10
- [PATCH v5 10/11] target/riscv: Add implied rule for counter delegation extensions, Atish Patra, 2025/01/10
- [PATCH v5 09/11] target/riscv: Invoke pmu init after feature enable, Atish Patra, 2025/01/10