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[PATCH v5 06/11] target/riscv: Add counter delegation definitions
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From: |
Atish Patra |
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Subject: |
[PATCH v5 06/11] target/riscv: Add counter delegation definitions |
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Date: |
Fri, 10 Jan 2025 00:21:34 -0800 |
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 8 +++++++-
target/riscv/machine.c | 1 +
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 08215efb096c..a936300103af 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -392,6 +392,7 @@ struct CPUArchState {
uint32_t scounteren;
uint32_t mcounteren;
+ uint32_t scountinhibit;
uint32_t mcountinhibit;
/* PMU cycle & instret privilege mode filtering */
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 6b1446fb7e99..73f7d37d80ee 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -210,6 +210,9 @@
#define CSR_SSTATEEN2 0x10E
#define CSR_SSTATEEN3 0x10F
+/* Supervisor Counter Delegation */
+#define CSR_SCOUNTINHIBIT 0x120
+
/* Supervisor Trap Handling */
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
@@ -779,6 +782,7 @@ typedef enum RISCVException {
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
#define MENVCFG_PMM (3ULL << 32)
+#define MENVCFG_CDE (1ULL << 60)
#define MENVCFG_ADUE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63)
@@ -826,7 +830,9 @@ typedef enum RISCVException {
#define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63
#define ISELECT_MASK_AIA 0x1ff
-/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
+/* [M|S|VS]SELCT value for Indirect CSR Access Extension */
+#define ISELECT_CD_FIRST 0x40
+#define ISELECT_CD_LAST 0x5f
#define ISELECT_MASK_SXCSRIND 0xfff
/* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index d81621010dc7..d8445244ab25 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -423,6 +423,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.siselect, RISCVCPU),
VMSTATE_UINT32(env.scounteren, RISCVCPU),
VMSTATE_UINT32(env.mcounteren, RISCVCPU),
+ VMSTATE_UINT32(env.scountinhibit, RISCVCPU),
VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
vmstate_pmu_ctr_state, PMUCTRState),
--
2.34.1
- [PATCH v5 00/11] Add RISC-V Counter delegation ISA extension support, Atish Patra, 2025/01/10
- [PATCH v5 01/11] target/riscv: Add properties for Indirect CSR Access extension, Atish Patra, 2025/01/10
- [PATCH v5 02/11] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2025/01/10
- [PATCH v5 03/11] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2025/01/10
- [PATCH v5 04/11] target/riscv: Support generic CSR indirect access, Atish Patra, 2025/01/10
- [PATCH v5 06/11] target/riscv: Add counter delegation definitions,
Atish Patra <=
- [PATCH v5 05/11] target/riscv: Add properties for counter delegation ISA extensions, Atish Patra, 2025/01/10
- [PATCH v5 07/11] target/riscv: Add select value range check for counter delegation, Atish Patra, 2025/01/10
- [PATCH v5 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Atish Patra, 2025/01/10
- [PATCH v5 08/11] target/riscv: Add counter delegation/configuration support, Atish Patra, 2025/01/10
- [PATCH v5 10/11] target/riscv: Add implied rule for counter delegation extensions, Atish Patra, 2025/01/10
- [PATCH v5 09/11] target/riscv: Invoke pmu init after feature enable, Atish Patra, 2025/01/10