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[PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take
From: |
Alistair Francis |
Subject: |
[PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu |
Date: |
Fri, 17 Jan 2025 15:55:28 +1000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Keep kvm_riscv_get_timebase_frequency() prototype aligned with
the other ones declared in "kvm_riscv.h", have it take a RISCVCPU
cpu as argument. Include "target/riscv/cpu-qom.h" which declares
the RISCVCPU typedef.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250112231344.34632-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm_riscv.h | 4 +++-
hw/riscv/virt.c | 2 +-
target/riscv/kvm/kvm-cpu.c | 4 ++--
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h
index 5851898868..b2bcd1041f 100644
--- a/target/riscv/kvm/kvm_riscv.h
+++ b/target/riscv/kvm/kvm_riscv.h
@@ -19,6 +19,8 @@
#ifndef QEMU_KVM_RISCV_H
#define QEMU_KVM_RISCV_H
+#include "target/riscv/cpu-qom.h"
+
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
@@ -28,6 +30,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t
group_shift,
void riscv_kvm_aplic_request(void *opaque, int irq, int level);
int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state);
void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
-uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs);
+uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu);
#endif
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2bc5a9dd98..9e8876be29 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -750,7 +750,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const
MemMapEntry *memmap,
qemu_fdt_add_subnode(ms->fdt, "/cpus");
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
kvm_enabled() ?
- kvm_riscv_get_timebase_frequency(first_cpu) :
+
kvm_riscv_get_timebase_frequency(RISCV_CPU(first_cpu)) :
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 11278ea778..23ce779359 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -758,11 +758,11 @@ static void kvm_riscv_put_regs_timer(CPUState *cs)
env->kvm_timer_dirty = false;
}
-uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs)
+uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu)
{
uint64_t reg;
- KVM_RISCV_GET_TIMER(cs, frequency, reg);
+ KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg);
return reg;
}
--
2.47.1
- [PULL 16/50] target/riscv: Add pointer masking tb flags, (continued)
- [PULL 16/50] target/riscv: Add pointer masking tb flags, Alistair Francis, 2025/01/17
- [PULL 17/50] target/riscv: Update address modify functions to take into account pointer masking, Alistair Francis, 2025/01/17
- [PULL 18/50] target/riscv: Apply pointer masking for virtualized memory accesses, Alistair Francis, 2025/01/17
- [PULL 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alistair Francis, 2025/01/17
- [PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig, Alistair Francis, 2025/01/17
- [PULL 21/50] target/riscv: Add Smrnmi CSRs, Alistair Francis, 2025/01/17
- [PULL 22/50] target/riscv: Handle Smrnmi interrupt and exception, Alistair Francis, 2025/01/17
- [PULL 23/50] target/riscv: Add Smrnmi mnret instruction, Alistair Francis, 2025/01/17
- [PULL 24/50] target/riscv: Add Smrnmi cpu extension, Alistair Francis, 2025/01/17
- [PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi, Alistair Francis, 2025/01/17
- [PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu,
Alistair Francis <=
- [PULL 27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu, Alistair Francis, 2025/01/17
- [PULL 28/50] target/riscv: Add properties for Indirect CSR Access extension, Alistair Francis, 2025/01/17
- [PULL 31/50] target/riscv: Support generic CSR indirect access, Alistair Francis, 2025/01/17
- [PULL 35/50] target/riscv: Add counter delegation/configuration support, Alistair Francis, 2025/01/17
- [PULL 30/50] target/riscv: Enable S*stateen bits for AIA, Alistair Francis, 2025/01/17
- [PULL 42/50] target/riscv: Implement Ssdbltrp exception handling, Alistair Francis, 2025/01/17
- [PULL 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Alistair Francis, 2025/01/17
- [PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg, Alistair Francis, 2025/01/17
- [PULL 37/50] target/riscv: Add implied rule for counter delegation extensions, Alistair Francis, 2025/01/17
- [PULL 34/50] target/riscv: Add select value range check for counter delegation, Alistair Francis, 2025/01/17