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[PULL 24/50] target/riscv: Add Smrnmi cpu extension
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From: |
Alistair Francis |
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Subject: |
[PULL 24/50] target/riscv: Add Smrnmi cpu extension |
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Date: |
Fri, 17 Jan 2025 15:55:26 +1000 |
From: Tommy Wu <tommy.wu@sifive.com>
This adds the properties for ISA extension Smrnmi.
Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set
mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
interrupts will be disabled. Since our current OpenSBI does not
support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for
now. We can re-enable it once OpenSBI includes proper support for it.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106054336.1878291-6-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/tcg/tcg-cpu.c | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eb06d06628..dace670e5e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
+ ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
@@ -1614,6 +1615,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
+ MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false),
MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 7f7283d52a..f94aa9f29e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1430,6 +1430,15 @@ static void riscv_init_max_cpu_extensions(Object *obj)
if (env->misa_mxl != MXL_RV32) {
isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
}
+
+ /*
+ * ext_smrnmi requires OpenSBI changes that our current
+ * image does not have. Disable it for now.
+ */
+ if (cpu->cfg.ext_smrnmi) {
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false);
+ qemu_log("Smrnmi is disabled in the 'max' type CPU\n");
+ }
}
static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
--
2.47.1
- [PULL 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0, (continued)
- [PULL 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alistair Francis, 2025/01/17
- [PULL 16/50] target/riscv: Add pointer masking tb flags, Alistair Francis, 2025/01/17
- [PULL 17/50] target/riscv: Update address modify functions to take into account pointer masking, Alistair Francis, 2025/01/17
- [PULL 18/50] target/riscv: Apply pointer masking for virtualized memory accesses, Alistair Francis, 2025/01/17
- [PULL 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alistair Francis, 2025/01/17
- [PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig, Alistair Francis, 2025/01/17
- [PULL 21/50] target/riscv: Add Smrnmi CSRs, Alistair Francis, 2025/01/17
- [PULL 22/50] target/riscv: Handle Smrnmi interrupt and exception, Alistair Francis, 2025/01/17
- [PULL 23/50] target/riscv: Add Smrnmi mnret instruction, Alistair Francis, 2025/01/17
- [PULL 24/50] target/riscv: Add Smrnmi cpu extension,
Alistair Francis <=
- [PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi, Alistair Francis, 2025/01/17
- [PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu, Alistair Francis, 2025/01/17
- [PULL 27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu, Alistair Francis, 2025/01/17
- [PULL 28/50] target/riscv: Add properties for Indirect CSR Access extension, Alistair Francis, 2025/01/17
- [PULL 31/50] target/riscv: Support generic CSR indirect access, Alistair Francis, 2025/01/17
- [PULL 35/50] target/riscv: Add counter delegation/configuration support, Alistair Francis, 2025/01/17
- [PULL 30/50] target/riscv: Enable S*stateen bits for AIA, Alistair Francis, 2025/01/17
- [PULL 42/50] target/riscv: Implement Ssdbltrp exception handling, Alistair Francis, 2025/01/17
- [PULL 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Alistair Francis, 2025/01/17
- [PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg, Alistair Francis, 2025/01/17