[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 19/50] target/riscv: Enable updates for pointer masking variables
|
From: |
Alistair Francis |
|
Subject: |
[PULL 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension |
|
Date: |
Fri, 17 Jan 2025 15:55:21 +1000 |
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106102346.1100149-8-baturo.alexey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 99588e219e..d9eb2c04c3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -193,11 +193,14 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
+ ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
+ ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
@@ -1595,9 +1598,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
+ MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
+ MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
+ MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false),
MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
--
2.47.1
- [PULL 09/50] target/riscv: add shgatpa, (continued)
- [PULL 09/50] target/riscv: add shgatpa, Alistair Francis, 2025/01/17
- [PULL 10/50] target/riscv/tcg: add sha, Alistair Francis, 2025/01/17
- [PULL 11/50] target/riscv: use RISCVException enum in exception helpers, Alistair Francis, 2025/01/17
- [PULL 12/50] target/riscv: add trace in riscv_raise_exception(), Alistair Francis, 2025/01/17
- [PULL 13/50] target/riscv: Remove obsolete pointer masking extension code., Alistair Francis, 2025/01/17
- [PULL 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alistair Francis, 2025/01/17
- [PULL 16/50] target/riscv: Add pointer masking tb flags, Alistair Francis, 2025/01/17
- [PULL 17/50] target/riscv: Update address modify functions to take into account pointer masking, Alistair Francis, 2025/01/17
- [PULL 18/50] target/riscv: Apply pointer masking for virtualized memory accesses, Alistair Francis, 2025/01/17
- [PULL 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension,
Alistair Francis <=
- [PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig, Alistair Francis, 2025/01/17
- [PULL 21/50] target/riscv: Add Smrnmi CSRs, Alistair Francis, 2025/01/17
- [PULL 22/50] target/riscv: Handle Smrnmi interrupt and exception, Alistair Francis, 2025/01/17
- [PULL 23/50] target/riscv: Add Smrnmi mnret instruction, Alistair Francis, 2025/01/17
- [PULL 24/50] target/riscv: Add Smrnmi cpu extension, Alistair Francis, 2025/01/17
- [PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi, Alistair Francis, 2025/01/17
- [PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu, Alistair Francis, 2025/01/17
- [PULL 27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu, Alistair Francis, 2025/01/17
- [PULL 28/50] target/riscv: Add properties for Indirect CSR Access extension, Alistair Francis, 2025/01/17
- [PULL 31/50] target/riscv: Support generic CSR indirect access, Alistair Francis, 2025/01/17