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[PULL 17/50] target/riscv: Update address modify functions to take into
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From: |
Alistair Francis |
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Subject: |
[PULL 17/50] target/riscv: Update address modify functions to take into account pointer masking |
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Date: |
Fri, 17 Jan 2025 15:55:19 +1000 |
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106102346.1100149-6-baturo.alexey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 22 ++++++++++++++++------
target/riscv/vector_helper.c | 16 ++++++++++++++++
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 26350b2826..698b74f7a8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -589,8 +589,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int
imm)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
- if (get_address_xl(ctx) == MXL_RV32) {
- tcg_gen_ext32u_tl(addr, addr);
+ if (ctx->addr_signed) {
+ tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl);
+ } else {
+ tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl);
}
return addr;
@@ -603,8 +605,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int
rs1, TCGv offs)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_add_tl(addr, src1, offs);
- if (get_xl(ctx) == MXL_RV32) {
- tcg_gen_ext32u_tl(addr, addr);
+ if (ctx->addr_signed) {
+ tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl);
+ } else {
+ tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl);
}
return addr;
@@ -1234,8 +1238,14 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
- ctx->addr_xl = 0;
- ctx->addr_signed = false;
+ if (get_xl(ctx) == MXL_RV32) {
+ ctx->addr_xl = 32;
+ ctx->addr_signed = false;
+ } else {
+ int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM);
+ ctx->addr_xl = 64 - riscv_pm_get_pmlen(pm_pmm);
+ ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND);
+ }
ctx->ztso = cpu->cfg.ext_ztso;
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cf5dd7f2e1..0eea124b66 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -107,6 +107,22 @@ static inline uint32_t vext_max_elems(uint32_t desc,
uint32_t log2_esz)
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ return addr;
+ }
+ RISCVPmPmm pmm = riscv_pm_get_pmm(env);
+ if (pmm == PMM_FIELD_DISABLED) {
+ return addr;
+ }
+ int pmlen = riscv_pm_get_pmlen(pmm);
+ bool signext = riscv_cpu_virt_mem_enabled(env);
+ addr = addr << pmlen;
+ /* sign/zero extend masked address by N-1 bit */
+ if (signext) {
+ addr = (target_long)addr >> pmlen;
+ } else {
+ addr = addr >> pmlen;
+ }
return addr;
}
--
2.47.1
- [PULL 07/50] target/riscv: add shvstvecd, (continued)
- [PULL 07/50] target/riscv: add shvstvecd, Alistair Francis, 2025/01/17
- [PULL 08/50] target/riscv: add shvsatpa, Alistair Francis, 2025/01/17
- [PULL 09/50] target/riscv: add shgatpa, Alistair Francis, 2025/01/17
- [PULL 10/50] target/riscv/tcg: add sha, Alistair Francis, 2025/01/17
- [PULL 11/50] target/riscv: use RISCVException enum in exception helpers, Alistair Francis, 2025/01/17
- [PULL 12/50] target/riscv: add trace in riscv_raise_exception(), Alistair Francis, 2025/01/17
- [PULL 13/50] target/riscv: Remove obsolete pointer masking extension code., Alistair Francis, 2025/01/17
- [PULL 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alistair Francis, 2025/01/17
- [PULL 16/50] target/riscv: Add pointer masking tb flags, Alistair Francis, 2025/01/17
- [PULL 17/50] target/riscv: Update address modify functions to take into account pointer masking,
Alistair Francis <=
- [PULL 18/50] target/riscv: Apply pointer masking for virtualized memory accesses, Alistair Francis, 2025/01/17
- [PULL 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alistair Francis, 2025/01/17
- [PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig, Alistair Francis, 2025/01/17
- [PULL 21/50] target/riscv: Add Smrnmi CSRs, Alistair Francis, 2025/01/17
- [PULL 22/50] target/riscv: Handle Smrnmi interrupt and exception, Alistair Francis, 2025/01/17
- [PULL 23/50] target/riscv: Add Smrnmi mnret instruction, Alistair Francis, 2025/01/17
- [PULL 24/50] target/riscv: Add Smrnmi cpu extension, Alistair Francis, 2025/01/17
- [PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi, Alistair Francis, 2025/01/17
- [PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu, Alistair Francis, 2025/01/17
- [PULL 27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu, Alistair Francis, 2025/01/17