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[PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig
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From: |
Alistair Francis |
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Subject: |
[PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig |
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Date: |
Fri, 17 Jan 2025 15:55:22 +1000 |
From: Tommy Wu <tommy.wu@sifive.com>
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106054336.1878291-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index a36d3fada3..ee7c908710 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -129,6 +129,7 @@ struct RISCVCPUConfig {
bool ext_ssaia;
bool ext_sscofpmf;
bool ext_smepmp;
+ bool ext_smrnmi;
bool ext_ssnpm;
bool ext_smnpm;
bool ext_smmpm;
--
2.47.1
- [PULL 10/50] target/riscv/tcg: add sha, (continued)
- [PULL 10/50] target/riscv/tcg: add sha, Alistair Francis, 2025/01/17
- [PULL 11/50] target/riscv: use RISCVException enum in exception helpers, Alistair Francis, 2025/01/17
- [PULL 12/50] target/riscv: add trace in riscv_raise_exception(), Alistair Francis, 2025/01/17
- [PULL 13/50] target/riscv: Remove obsolete pointer masking extension code., Alistair Francis, 2025/01/17
- [PULL 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alistair Francis, 2025/01/17
- [PULL 16/50] target/riscv: Add pointer masking tb flags, Alistair Francis, 2025/01/17
- [PULL 17/50] target/riscv: Update address modify functions to take into account pointer masking, Alistair Francis, 2025/01/17
- [PULL 18/50] target/riscv: Apply pointer masking for virtualized memory accesses, Alistair Francis, 2025/01/17
- [PULL 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alistair Francis, 2025/01/17
- [PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig,
Alistair Francis <=
- [PULL 21/50] target/riscv: Add Smrnmi CSRs, Alistair Francis, 2025/01/17
- [PULL 22/50] target/riscv: Handle Smrnmi interrupt and exception, Alistair Francis, 2025/01/17
- [PULL 23/50] target/riscv: Add Smrnmi mnret instruction, Alistair Francis, 2025/01/17
- [PULL 24/50] target/riscv: Add Smrnmi cpu extension, Alistair Francis, 2025/01/17
- [PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi, Alistair Francis, 2025/01/17
- [PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu, Alistair Francis, 2025/01/17
- [PULL 27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu, Alistair Francis, 2025/01/17
- [PULL 28/50] target/riscv: Add properties for Indirect CSR Access extension, Alistair Francis, 2025/01/17
- [PULL 31/50] target/riscv: Support generic CSR indirect access, Alistair Francis, 2025/01/17
- [PULL 35/50] target/riscv: Add counter delegation/configuration support, Alistair Francis, 2025/01/17