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[PULL 36/50] target/riscv: Invoke pmu init after feature enable
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From: |
Alistair Francis |
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Subject: |
[PULL 36/50] target/riscv: Invoke pmu init after feature enable |
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Date: |
Fri, 17 Jan 2025 15:55:38 +1000 |
From: Atish Patra <atishp@rivosinc.com>
The dependant ISA features are enabled at the end of cpu_realize
in finalize_features. Thus, PMU init should be invoked after that
only. Move the init invocation to riscv_tcg_cpu_finalize_features.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-9-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f94aa9f29e..48be24bbbe 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -963,6 +963,20 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
**errp)
error_propagate(errp, local_err);
return;
}
+#ifndef CONFIG_USER_ONLY
+ if (cpu->cfg.pmu_mask) {
+ riscv_pmu_init(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (cpu->cfg.ext_sscofpmf) {
+ cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ riscv_pmu_timer_cb, cpu);
+ }
+ }
+#endif
}
void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
@@ -1010,7 +1024,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
**errp)
#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
- Error *local_err = NULL;
tcg_cflags_set(CPU(cs), CF_PCREL);
@@ -1018,19 +1031,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
**errp)
riscv_timer_init(cpu);
}
- if (cpu->cfg.pmu_mask) {
- riscv_pmu_init(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return false;
- }
-
- if (cpu->cfg.ext_sscofpmf) {
- cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- riscv_pmu_timer_cb, cpu);
- }
- }
-
/* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */
if (riscv_has_ext(env, RVH)) {
env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP;
--
2.47.1
- [PULL 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, (continued)
- [PULL 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Alistair Francis, 2025/01/17
- [PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg, Alistair Francis, 2025/01/17
- [PULL 37/50] target/riscv: Add implied rule for counter delegation extensions, Alistair Francis, 2025/01/17
- [PULL 34/50] target/riscv: Add select value range check for counter delegation, Alistair Francis, 2025/01/17
- [PULL 39/50] target/riscv: Fix henvcfg potentially containing stale bits, Alistair Francis, 2025/01/17
- [PULL 40/50] target/riscv: Add Ssdbltrp CSRs handling, Alistair Francis, 2025/01/17
- [PULL 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/17
- [PULL 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/17
- [PULL 32/50] target/riscv: Add properties for counter delegation ISA extensions, Alistair Francis, 2025/01/17
- [PULL 33/50] target/riscv: Add counter delegation definitions, Alistair Francis, 2025/01/17
- [PULL 36/50] target/riscv: Invoke pmu init after feature enable,
Alistair Francis <=
- [PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch, Alistair Francis, 2025/01/17
- [PULL 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache, Alistair Francis, 2025/01/17
- [PULL 46/50] target/riscv: Implement Smdbltrp behavior, Alistair Francis, 2025/01/17
- [PULL 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch, Alistair Francis, 2025/01/17
- [PULL 44/50] target/riscv: Add Smdbltrp CSRs handling, Alistair Francis, 2025/01/17
- [PULL 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events, Alistair Francis, 2025/01/17