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[PULL 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events
From: |
Alistair Francis |
Subject: |
[PULL 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events |
Date: |
Fri, 17 Jan 2025 15:55:52 +1000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250116223609.81594-1-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/char/riscv_htif.c | 15 +++------------
hw/char/trace-events | 4 ++++
2 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 11a0e1a7b7..ec5db5a597 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -32,14 +32,7 @@
#include "exec/tswap.h"
#include "system/dma.h"
#include "system/runstate.h"
-
-#define RISCV_DEBUG_HTIF 0
-#define HTIF_DEBUG(fmt, ...)
\
- do {
\
- if (RISCV_DEBUG_HTIF) {
\
- qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__,
##__VA_ARGS__);\
- }
\
- } while (0)
+#include "trace.h"
#define HTIF_DEV_SHIFT 56
#define HTIF_CMD_SHIFT 48
@@ -159,8 +152,7 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t
val_written)
uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
int resp = 0;
- HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64
- " -payload: %016" PRIx64 "\n", device, cmd, payload & 0xFF, payload);
+ trace_htif_uart_write_to_host(device, cmd, payload);
/*
* Currently, there is a fixed mapping of devices:
@@ -251,8 +243,7 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t
val_written)
}
} else {
qemu_log("HTIF unknown device or command\n");
- HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64
- " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload);
+ trace_htif_uart_unknown_device_command(device, cmd, payload);
}
/*
* Latest bbl does not set fromhost to 0 if there is a value in tohost.
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 3ee7cfcdff..b2e3d25ae3 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -136,3 +136,7 @@ stm32f2xx_usart_read(char *id, unsigned size, uint64_t ofs,
uint64_t val) " %s s
stm32f2xx_usart_write(char *id, unsigned size, uint64_t ofs, uint64_t val) "%s
size %d ofs 0x%02" PRIx64 " <- 0x%02" PRIx64
stm32f2xx_usart_drop(char *id) " %s dropping the chars"
stm32f2xx_usart_receive(char *id, uint8_t chr) " %s receiving '%c'"
+
+# riscv_htif.c
+htif_uart_write_to_host(uint8_t device, uint8_t cmd, uint64_t payload)
"device: %u cmd: %02u payload: %016" PRIx64
+htif_uart_unknown_device_command(uint8_t device, uint8_t cmd, uint64_t
payload) "device: %u cmd: %02u payload: %016" PRIx64
--
2.47.1
- [PULL 32/50] target/riscv: Add properties for counter delegation ISA extensions, (continued)
- [PULL 32/50] target/riscv: Add properties for counter delegation ISA extensions, Alistair Francis, 2025/01/17
- [PULL 33/50] target/riscv: Add counter delegation definitions, Alistair Francis, 2025/01/17
- [PULL 36/50] target/riscv: Invoke pmu init after feature enable, Alistair Francis, 2025/01/17
- [PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch, Alistair Francis, 2025/01/17
- [PULL 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache, Alistair Francis, 2025/01/17
- [PULL 46/50] target/riscv: Implement Smdbltrp behavior, Alistair Francis, 2025/01/17
- [PULL 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch, Alistair Francis, 2025/01/17
- [PULL 44/50] target/riscv: Add Smdbltrp CSRs handling, Alistair Francis, 2025/01/17
- [PULL 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events,
Alistair Francis <=