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[PULL 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behav
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From: |
Alistair Francis |
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Subject: |
[PULL 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior |
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Date: |
Fri, 17 Jan 2025 15:55:47 +1000 |
From: Clément Léger <cleger@rivosinc.com>
When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
when executing sret if executed in M-mode. When executing mret/mnret,
SSTATUS.MDT is cleared.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250110125441.3208676-8-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 59c4bf28ed..ce1256f439 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -306,6 +306,9 @@ target_ulong helper_sret(CPURISCVState *env)
}
mstatus = set_field(mstatus, MSTATUS_SDT, 0);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >= PRV_M) {
+ mstatus = set_field(mstatus, MSTATUS_MDT, 0);
+ }
if (env->priv_ver >= PRIV_VERSION_1_12_0) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
}
@@ -391,6 +394,9 @@ target_ulong helper_mret(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ mstatus = set_field(mstatus, MSTATUS_MDT, 0);
+ }
if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
}
@@ -436,6 +442,12 @@ target_ulong helper_mnret(CPURISCVState *env)
env->mstatus = ssdbltrp_mxret(env, env->mstatus, prev_priv, prev_virt);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ if (prev_priv < PRV_M) {
+ env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 0);
+ }
+ }
+
if (riscv_has_ext(env, RVH) && prev_virt) {
riscv_cpu_swap_hypervisor_regs(env);
}
--
2.47.1
- [PULL 35/50] target/riscv: Add counter delegation/configuration support, (continued)
- [PULL 35/50] target/riscv: Add counter delegation/configuration support, Alistair Francis, 2025/01/17
- [PULL 30/50] target/riscv: Enable S*stateen bits for AIA, Alistair Francis, 2025/01/17
- [PULL 42/50] target/riscv: Implement Ssdbltrp exception handling, Alistair Francis, 2025/01/17
- [PULL 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Alistair Francis, 2025/01/17
- [PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg, Alistair Francis, 2025/01/17
- [PULL 37/50] target/riscv: Add implied rule for counter delegation extensions, Alistair Francis, 2025/01/17
- [PULL 34/50] target/riscv: Add select value range check for counter delegation, Alistair Francis, 2025/01/17
- [PULL 39/50] target/riscv: Fix henvcfg potentially containing stale bits, Alistair Francis, 2025/01/17
- [PULL 40/50] target/riscv: Add Ssdbltrp CSRs handling, Alistair Francis, 2025/01/17
- [PULL 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/17
- [PULL 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior,
Alistair Francis <=
- [PULL 32/50] target/riscv: Add properties for counter delegation ISA extensions, Alistair Francis, 2025/01/17
- [PULL 33/50] target/riscv: Add counter delegation definitions, Alistair Francis, 2025/01/17
- [PULL 36/50] target/riscv: Invoke pmu init after feature enable, Alistair Francis, 2025/01/17
- [PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch, Alistair Francis, 2025/01/17
- [PULL 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache, Alistair Francis, 2025/01/17
- [PULL 46/50] target/riscv: Implement Smdbltrp behavior, Alistair Francis, 2025/01/17
- [PULL 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch, Alistair Francis, 2025/01/17
- [PULL 44/50] target/riscv: Add Smdbltrp CSRs handling, Alistair Francis, 2025/01/17