[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v8 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret beh
From: |
Clément Léger |
Subject: |
[PATCH v8 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret behavior |
Date: |
Fri, 10 Jan 2025 13:54:38 +0100 |
When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
when executing sret if executed in M-mode. When executing mret/mnret,
SSTATUS.MDT is cleared.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 59c4bf28ed..ce1256f439 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -306,6 +306,9 @@ target_ulong helper_sret(CPURISCVState *env)
}
mstatus = set_field(mstatus, MSTATUS_SDT, 0);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >= PRV_M) {
+ mstatus = set_field(mstatus, MSTATUS_MDT, 0);
+ }
if (env->priv_ver >= PRIV_VERSION_1_12_0) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
}
@@ -391,6 +394,9 @@ target_ulong helper_mret(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ mstatus = set_field(mstatus, MSTATUS_MDT, 0);
+ }
if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
}
@@ -436,6 +442,12 @@ target_ulong helper_mnret(CPURISCVState *env)
env->mstatus = ssdbltrp_mxret(env, env->mstatus, prev_priv, prev_virt);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ if (prev_priv < PRV_M) {
+ env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 0);
+ }
+ }
+
if (riscv_has_ext(env, RVH) && prev_virt) {
riscv_cpu_swap_hypervisor_regs(env);
}
--
2.47.1
- [PATCH v8 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions, Clément Léger, 2025/01/10
- [PATCH v8 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret behavior,
Clément Léger <=
- [PATCH v8 4/9] target/riscv: Implement Ssdbltrp exception handling, Clément Léger, 2025/01/10
- [PATCH v8 6/9] target/riscv: Add Smdbltrp CSRs handling, Clément Léger, 2025/01/10
- [PATCH v8 9/9] target/riscv: Add Smdbltrp ISA extension enable switch, Clément Léger, 2025/01/10
- [PATCH v8 3/9] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Clément Léger, 2025/01/10
- [PATCH v8 2/9] target/riscv: Add Ssdbltrp CSRs handling, Clément Léger, 2025/01/10
- [PATCH v8 1/9] target/riscv: Fix henvcfg potentially containing stale bits, Clément Léger, 2025/01/10
- [PATCH v8 5/9] target/riscv: Add Ssdbltrp ISA extension enable switch, Clément Léger, 2025/01/10
- [PATCH v8 8/9] target/riscv: Implement Smdbltrp behavior, Clément Léger, 2025/01/10