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[PATCH v8 6/9] target/riscv: Add Smdbltrp CSRs handling
From: |
Clément Léger |
Subject: |
[PATCH v8 6/9] target/riscv: Add Smdbltrp CSRs handling |
Date: |
Fri, 10 Jan 2025 13:54:37 +0100 |
Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior.
Also set MDT to 1 at reset according to the specification.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 +++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 13 +++++++++++++
4 files changed, 18 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9e1ce0e1f1..e3ed11b0fd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1064,6 +1064,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType
type)
env->mstatus_hs = set_field(env->mstatus_hs,
MSTATUS64_UXL, env->misa_mxl);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);
+ }
}
env->mcause = 0;
env->miclaim = MIP_SGEIP;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a3acda4bc8..f97c48a394 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -559,6 +559,7 @@
#define MSTATUS_MPELP 0x020000000000 /* zicfilp */
#define MSTATUS_GVA 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
+#define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */
#define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 20e11a5bdd..aef896ba00 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_smcsrind;
bool ext_sscsrind;
bool ext_ssdbltrp;
+ bool ext_smdbltrp;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4aded3f00c..afb7544f07 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1954,6 +1954,13 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
}
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ mask |= MSTATUS_MDT;
+ if ((val & MSTATUS_MDT) != 0) {
+ val &= ~MSTATUS_MIE;
+ }
+ }
+
if (xl != MXL_RV32 || env->debugger) {
if (riscv_has_ext(env, RVH)) {
mask |= MSTATUS_MPV | MSTATUS_GVA;
@@ -1996,6 +2003,12 @@ static RISCVException write_mstatush(CPURISCVState *env,
int csrno,
uint64_t valh = (uint64_t)val << 32;
uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0;
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ mask |= MSTATUS_MDT;
+ if ((valh & MSTATUS_MDT) != 0) {
+ mask |= MSTATUS_MIE;
+ }
+ }
env->mstatus = (env->mstatus & ~mask) | (valh & mask);
return RISCV_EXCP_NONE;
--
2.47.1
- [PATCH v8 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions, Clément Léger, 2025/01/10
- [PATCH v8 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Clément Léger, 2025/01/10
- [PATCH v8 4/9] target/riscv: Implement Ssdbltrp exception handling, Clément Léger, 2025/01/10
- [PATCH v8 6/9] target/riscv: Add Smdbltrp CSRs handling,
Clément Léger <=
- [PATCH v8 9/9] target/riscv: Add Smdbltrp ISA extension enable switch, Clément Léger, 2025/01/10
- [PATCH v8 3/9] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Clément Léger, 2025/01/10
- [PATCH v8 2/9] target/riscv: Add Ssdbltrp CSRs handling, Clément Léger, 2025/01/10
- [PATCH v8 1/9] target/riscv: Fix henvcfg potentially containing stale bits, Clément Léger, 2025/01/10
- [PATCH v8 5/9] target/riscv: Add Ssdbltrp ISA extension enable switch, Clément Léger, 2025/01/10
- [PATCH v8 8/9] target/riscv: Implement Smdbltrp behavior, Clément Léger, 2025/01/10