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[PATCH v8 9/9] target/riscv: Add Smdbltrp ISA extension enable switch
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From: |
Clément Léger |
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Subject: |
[PATCH v8 9/9] target/riscv: Add Smdbltrp ISA extension enable switch |
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Date: |
Fri, 10 Jan 2025 13:54:40 +0100 |
Add the switch to enable the Smdbltrp ISA extension.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e3ed11b0fd..bddf1ba75e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind),
+ ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
@@ -1626,6 +1627,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
+ MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false),
MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
--
2.47.1
- [PATCH v8 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions, Clément Léger, 2025/01/10
- [PATCH v8 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Clément Léger, 2025/01/10
- [PATCH v8 4/9] target/riscv: Implement Ssdbltrp exception handling, Clément Léger, 2025/01/10
- [PATCH v8 6/9] target/riscv: Add Smdbltrp CSRs handling, Clément Léger, 2025/01/10
- [PATCH v8 9/9] target/riscv: Add Smdbltrp ISA extension enable switch,
Clément Léger <=
- [PATCH v8 3/9] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Clément Léger, 2025/01/10
- [PATCH v8 2/9] target/riscv: Add Ssdbltrp CSRs handling, Clément Léger, 2025/01/10
- [PATCH v8 1/9] target/riscv: Fix henvcfg potentially containing stale bits, Clément Léger, 2025/01/10
- [PATCH v8 5/9] target/riscv: Add Ssdbltrp ISA extension enable switch, Clément Léger, 2025/01/10
- [PATCH v8 8/9] target/riscv: Implement Smdbltrp behavior, Clément Léger, 2025/01/10