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[PULL 32/48] hw/core/clock: trace clock values in Hz instead of ns
From: |
Peter Maydell |
Subject: |
[PULL 32/48] hw/core/clock: trace clock values in Hz instead of ns |
Date: |
Tue, 27 Oct 2020 11:44:22 +0000 |
From: Luc Michel <luc@lmichel.fr>
The nanosecond unit greatly limits the dynamic range we can display in
clock value traces, for values in the order of 1GHz and more. The
internal representation can go way beyond this value and it is quite
common for today's clocks to be within those ranges.
For example, a frequency between 500MHz+ and 1GHz will be displayed as
1ns. Beyond 1GHz, it will show up as 0ns.
Replace nanosecond periods traces with frequencies in the Hz unit
to have more dynamic range in the trace output.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/core/clock.c | 6 +++---
hw/core/trace-events | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/core/clock.c b/hw/core/clock.c
index f866717a835..8c6af223e7c 100644
--- a/hw/core/clock.c
+++ b/hw/core/clock.c
@@ -54,8 +54,8 @@ bool clock_set(Clock *clk, uint64_t period)
if (clk->period == period) {
return false;
}
- trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
- CLOCK_PERIOD_TO_NS(period));
+ trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period),
+ CLOCK_PERIOD_TO_HZ(period));
clk->period = period;
return true;
@@ -69,7 +69,7 @@ static void clock_propagate_period(Clock *clk, bool
call_callbacks)
if (child->period != clk->period) {
child->period = clk->period;
trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
- CLOCK_PERIOD_TO_NS(clk->period),
+ CLOCK_PERIOD_TO_HZ(clk->period),
call_callbacks);
if (call_callbacks && child->callback) {
child->callback(child->callback_opaque);
diff --git a/hw/core/trace-events b/hw/core/trace-events
index 1ac60ede6b7..360ddeb2c87 100644
--- a/hw/core/trace-events
+++ b/hw/core/trace-events
@@ -31,6 +31,6 @@ resettable_transitional_function(void *obj, const char
*objtype) "obj=%p(%s)"
# clock.c
clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
clock_disconnect(const char *clk) "'%s'"
-clock_set(const char *clk, uint64_t old, uint64_t new) "'%s',
ns=%"PRIu64"->%"PRIu64
+clock_set(const char *clk, uint64_t old, uint64_t new) "'%s',
%"PRIu64"Hz->%"PRIu64"Hz"
clock_propagate(const char *clk) "'%s'"
-clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s',
src='%s', ns=%"PRIu64", cb=%d"
+clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s',
src='%s', val=%"PRIu64"Hz cb=%d"
--
2.20.1
- [PULL 22/48] hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type, (continued)
- [PULL 22/48] hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type, Peter Maydell, 2020/10/27
- [PULL 24/48] hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs, Peter Maydell, 2020/10/27
- [PULL 23/48] hw/arm/bcm2836: Introduce BCM283XClass::core_count, Peter Maydell, 2020/10/27
- [PULL 26/48] hw/arm/bcm2836: Introduce the BCM2835 SoC, Peter Maydell, 2020/10/27
- [PULL 25/48] hw/arm/bcm2836: Split out common realize() code, Peter Maydell, 2020/10/27
- [PULL 28/48] hw/arm/raspi: Add the Raspberry Pi Zero machine, Peter Maydell, 2020/10/27
- [PULL 27/48] hw/arm/raspi: Add the Raspberry Pi A+ machine, Peter Maydell, 2020/10/27
- [PULL 33/48] hw/arm/raspi: fix CPRMAN base address, Peter Maydell, 2020/10/27
- [PULL 31/48] hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro, Peter Maydell, 2020/10/27
- [PULL 29/48] hw/arm/raspi: Add the Raspberry Pi 3 model A+, Peter Maydell, 2020/10/27
- [PULL 32/48] hw/core/clock: trace clock values in Hz instead of ns,
Peter Maydell <=
- [PULL 30/48] arm/trace: Fix hex printing, Peter Maydell, 2020/10/27
- [PULL 34/48] hw/arm/raspi: add a skeleton implementation of the CPRMAN, Peter Maydell, 2020/10/27
- [PULL 35/48] hw/misc/bcm2835_cprman: add a PLL skeleton implementation, Peter Maydell, 2020/10/27
- [PULL 36/48] hw/misc/bcm2835_cprman: implement PLLs behaviour, Peter Maydell, 2020/10/27
- [PULL 37/48] hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation, Peter Maydell, 2020/10/27
- [PULL 38/48] hw/misc/bcm2835_cprman: implement PLL channels behaviour, Peter Maydell, 2020/10/27
- [PULL 39/48] hw/misc/bcm2835_cprman: add a clock mux skeleton implementation, Peter Maydell, 2020/10/27
- [PULL 42/48] hw/misc/bcm2835_cprman: add sane reset values to the registers, Peter Maydell, 2020/10/27
- [PULL 40/48] hw/misc/bcm2835_cprman: implement clock mux behaviour, Peter Maydell, 2020/10/27
- [PULL 41/48] hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer, Peter Maydell, 2020/10/27