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[PULL 26/48] hw/arm/bcm2836: Introduce the BCM2835 SoC
From: |
Peter Maydell |
Subject: |
[PULL 26/48] hw/arm/bcm2836: Introduce the BCM2835 SoC |
Date: |
Tue, 27 Oct 2020 11:44:16 +0000 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-7-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/bcm2836.h | 1 +
hw/arm/bcm2836.c | 34 ++++++++++++++++++++++++++++++++++
hw/arm/raspi.c | 2 ++
3 files changed, 37 insertions(+)
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index 43e9f8cd0ef..6f90cabfa3a 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -26,6 +26,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
* them, code using these devices should always handle them via the
* BCM283x base class, so they have no BCM2836(obj) etc macros.
*/
+#define TYPE_BCM2835 "bcm2835"
#define TYPE_BCM2836 "bcm2836"
#define TYPE_BCM2837 "bcm2837"
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 7d975cf2f53..de7ade2878e 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -89,6 +89,25 @@ static bool bcm283x_common_realize(DeviceState *dev, Error
**errp)
return true;
}
+static void bcm2835_realize(DeviceState *dev, Error **errp)
+{
+ BCM283XState *s = BCM283X(dev);
+
+ if (!bcm283x_common_realize(dev, errp)) {
+ return;
+ }
+
+ if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
+ return;
+ }
+
+ /* Connect irq/fiq outputs from the interrupt controller. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
+ qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
+ qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
+}
+
static void bcm2836_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
@@ -159,6 +178,17 @@ static void bcm283x_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
}
+static void bcm2835_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ BCM283XClass *bc = BCM283X_CLASS(oc);
+
+ bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
+ bc->core_count = 1;
+ bc->peri_base = 0x20000000;
+ dc->realize = bcm2835_realize;
+};
+
static void bcm2836_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -189,6 +219,10 @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
static const TypeInfo bcm283x_types[] = {
{
+ .name = TYPE_BCM2835,
+ .parent = TYPE_BCM283X,
+ .class_init = bcm2835_class_init,
+ }, {
.name = TYPE_BCM2836,
.parent = TYPE_BCM283X,
.class_init = bcm2836_class_init,
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index b5b30f0f38f..30fafa59ecb 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -70,6 +70,7 @@ FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
FIELD(REV_CODE, STYLE, 23, 1);
typedef enum RaspiProcessorId {
+ PROCESSOR_ID_BCM2835 = 0,
PROCESSOR_ID_BCM2836 = 1,
PROCESSOR_ID_BCM2837 = 2,
} RaspiProcessorId;
@@ -78,6 +79,7 @@ static const struct {
const char *type;
int cores_count;
} soc_property[] = {
+ [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1},
[PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
[PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
};
--
2.20.1
- [PULL 16/48] hw/timer: Adding watchdog for NPCM7XX Timer., (continued)
- [PULL 16/48] hw/timer: Adding watchdog for NPCM7XX Timer., Peter Maydell, 2020/10/27
- [PULL 11/48] linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND, Peter Maydell, 2020/10/27
- [PULL 12/48] tests/tcg/aarch64: Add bti smoke tests, Peter Maydell, 2020/10/27
- [PULL 18/48] hw/arm/npcm7xx: Add EHCI and OHCI controllers, Peter Maydell, 2020/10/27
- [PULL 20/48] hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly, Peter Maydell, 2020/10/27
- [PULL 21/48] hw/arm/bcm2836: Restrict BCM283XInfo declaration to C source, Peter Maydell, 2020/10/27
- [PULL 19/48] hw/gpio: Add GPIO model for Nuvoton NPCM7xx, Peter Maydell, 2020/10/27
- [PULL 22/48] hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type, Peter Maydell, 2020/10/27
- [PULL 24/48] hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs, Peter Maydell, 2020/10/27
- [PULL 23/48] hw/arm/bcm2836: Introduce BCM283XClass::core_count, Peter Maydell, 2020/10/27
- [PULL 26/48] hw/arm/bcm2836: Introduce the BCM2835 SoC,
Peter Maydell <=
- [PULL 25/48] hw/arm/bcm2836: Split out common realize() code, Peter Maydell, 2020/10/27
- [PULL 28/48] hw/arm/raspi: Add the Raspberry Pi Zero machine, Peter Maydell, 2020/10/27
- [PULL 27/48] hw/arm/raspi: Add the Raspberry Pi A+ machine, Peter Maydell, 2020/10/27
- [PULL 33/48] hw/arm/raspi: fix CPRMAN base address, Peter Maydell, 2020/10/27
- [PULL 31/48] hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro, Peter Maydell, 2020/10/27
- [PULL 29/48] hw/arm/raspi: Add the Raspberry Pi 3 model A+, Peter Maydell, 2020/10/27
- [PULL 32/48] hw/core/clock: trace clock values in Hz instead of ns, Peter Maydell, 2020/10/27
- [PULL 30/48] arm/trace: Fix hex printing, Peter Maydell, 2020/10/27
- [PULL 34/48] hw/arm/raspi: add a skeleton implementation of the CPRMAN, Peter Maydell, 2020/10/27
- [PULL 35/48] hw/misc/bcm2835_cprman: add a PLL skeleton implementation, Peter Maydell, 2020/10/27