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[PULL 23/48] hw/arm/bcm2836: Introduce BCM283XClass::core_count
From: |
Peter Maydell |
Subject: |
[PULL 23/48] hw/arm/bcm2836: Introduce BCM283XClass::core_count |
Date: |
Tue, 27 Oct 2020 11:44:13 +0000 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The BCM2835 has only one core. Introduce the core_count field to
be able to use values different than BCM283X_NCPUS (4).
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/bcm2836.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 8f921d8e904..c5d46a8e805 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -23,6 +23,7 @@ typedef struct BCM283XClass {
/*< public >*/
const char *name;
const char *cpu_type;
+ unsigned core_count;
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
@@ -39,7 +40,7 @@ static void bcm2836_init(Object *obj)
BCM283XClass *bc = BCM283X_GET_CLASS(obj);
int n;
- for (n = 0; n < BCM283X_NCPUS; n++) {
+ for (n = 0; n < bc->core_count; n++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
bc->cpu_type);
}
@@ -149,6 +150,7 @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
+ bc->core_count = BCM283X_NCPUS;
bc->peri_base = 0x3f000000;
bc->ctrl_base = 0x40000000;
bc->clusterid = 0xf;
@@ -163,6 +165,7 @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
+ bc->core_count = BCM283X_NCPUS;
bc->peri_base = 0x3f000000;
bc->ctrl_base = 0x40000000;
bc->clusterid = 0x0;
--
2.20.1
- [PULL 17/48] hw/misc: Add npcm7xx random number generator, (continued)
- [PULL 17/48] hw/misc: Add npcm7xx random number generator, Peter Maydell, 2020/10/27
- [PULL 16/48] hw/timer: Adding watchdog for NPCM7XX Timer., Peter Maydell, 2020/10/27
- [PULL 11/48] linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND, Peter Maydell, 2020/10/27
- [PULL 12/48] tests/tcg/aarch64: Add bti smoke tests, Peter Maydell, 2020/10/27
- [PULL 18/48] hw/arm/npcm7xx: Add EHCI and OHCI controllers, Peter Maydell, 2020/10/27
- [PULL 20/48] hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly, Peter Maydell, 2020/10/27
- [PULL 21/48] hw/arm/bcm2836: Restrict BCM283XInfo declaration to C source, Peter Maydell, 2020/10/27
- [PULL 19/48] hw/gpio: Add GPIO model for Nuvoton NPCM7xx, Peter Maydell, 2020/10/27
- [PULL 22/48] hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type, Peter Maydell, 2020/10/27
- [PULL 24/48] hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs, Peter Maydell, 2020/10/27
- [PULL 23/48] hw/arm/bcm2836: Introduce BCM283XClass::core_count,
Peter Maydell <=
- [PULL 26/48] hw/arm/bcm2836: Introduce the BCM2835 SoC, Peter Maydell, 2020/10/27
- [PULL 25/48] hw/arm/bcm2836: Split out common realize() code, Peter Maydell, 2020/10/27
- [PULL 28/48] hw/arm/raspi: Add the Raspberry Pi Zero machine, Peter Maydell, 2020/10/27
- [PULL 27/48] hw/arm/raspi: Add the Raspberry Pi A+ machine, Peter Maydell, 2020/10/27
- [PULL 33/48] hw/arm/raspi: fix CPRMAN base address, Peter Maydell, 2020/10/27
- [PULL 31/48] hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro, Peter Maydell, 2020/10/27
- [PULL 29/48] hw/arm/raspi: Add the Raspberry Pi 3 model A+, Peter Maydell, 2020/10/27
- [PULL 32/48] hw/core/clock: trace clock values in Hz instead of ns, Peter Maydell, 2020/10/27
- [PULL 30/48] arm/trace: Fix hex printing, Peter Maydell, 2020/10/27
- [PULL 34/48] hw/arm/raspi: add a skeleton implementation of the CPRMAN, Peter Maydell, 2020/10/27