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[PULL 38/48] hw/misc/bcm2835_cprman: implement PLL channels behaviour
From: |
Peter Maydell |
Subject: |
[PULL 38/48] hw/misc/bcm2835_cprman: implement PLL channels behaviour |
Date: |
Tue, 27 Oct 2020 11:44:28 +0000 |
From: Luc Michel <luc@lmichel.fr>
A PLL channel is able to further divide the generated PLL frequency.
The divider is given in the CTRL_A2W register. Some channels have an
additional fixed divider which is always applied to the signal.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/bcm2835_cprman.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
index 12fa78181b5..71c1d7b9e7b 100644
--- a/hw/misc/bcm2835_cprman.c
+++ b/hw/misc/bcm2835_cprman.c
@@ -134,9 +134,40 @@ static const TypeInfo cprman_pll_info = {
/* PLL channel */
+static bool pll_channel_is_enabled(CprmanPllChannelState *channel)
+{
+ /*
+ * XXX I'm not sure of the purpose of the LOAD field. The Linux driver does
+ * not set it when enabling the channel, but does clear it when disabling
+ * it.
+ */
+ return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE)
+ && !(*channel->reg_cm & channel->hold_mask);
+}
+
static void pll_channel_update(CprmanPllChannelState *channel)
{
- clock_update(channel->out, 0);
+ uint64_t freq, div;
+
+ if (!pll_channel_is_enabled(channel)) {
+ clock_update(channel->out, 0);
+ return;
+ }
+
+ div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV);
+
+ if (!div) {
+ /*
+ * It seems that when the divider value is 0, it is considered as
+ * being maximum by the hardware (see the Linux driver).
+ */
+ div = R_A2W_PLLx_CHANNELy_DIV_MASK;
+ }
+
+ /* Some channels have an additional fixed divider */
+ freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider);
+
+ clock_update_hz(channel->out, freq);
}
/* Update a PLL and all its channels */
--
2.20.1
- [PULL 27/48] hw/arm/raspi: Add the Raspberry Pi A+ machine, (continued)
- [PULL 27/48] hw/arm/raspi: Add the Raspberry Pi A+ machine, Peter Maydell, 2020/10/27
- [PULL 33/48] hw/arm/raspi: fix CPRMAN base address, Peter Maydell, 2020/10/27
- [PULL 31/48] hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro, Peter Maydell, 2020/10/27
- [PULL 29/48] hw/arm/raspi: Add the Raspberry Pi 3 model A+, Peter Maydell, 2020/10/27
- [PULL 32/48] hw/core/clock: trace clock values in Hz instead of ns, Peter Maydell, 2020/10/27
- [PULL 30/48] arm/trace: Fix hex printing, Peter Maydell, 2020/10/27
- [PULL 34/48] hw/arm/raspi: add a skeleton implementation of the CPRMAN, Peter Maydell, 2020/10/27
- [PULL 35/48] hw/misc/bcm2835_cprman: add a PLL skeleton implementation, Peter Maydell, 2020/10/27
- [PULL 36/48] hw/misc/bcm2835_cprman: implement PLLs behaviour, Peter Maydell, 2020/10/27
- [PULL 37/48] hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation, Peter Maydell, 2020/10/27
- [PULL 38/48] hw/misc/bcm2835_cprman: implement PLL channels behaviour,
Peter Maydell <=
- [PULL 39/48] hw/misc/bcm2835_cprman: add a clock mux skeleton implementation, Peter Maydell, 2020/10/27
- [PULL 42/48] hw/misc/bcm2835_cprman: add sane reset values to the registers, Peter Maydell, 2020/10/27
- [PULL 40/48] hw/misc/bcm2835_cprman: implement clock mux behaviour, Peter Maydell, 2020/10/27
- [PULL 41/48] hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer, Peter Maydell, 2020/10/27
- [PULL 44/48] hw/arm/bcm2835_peripherals: connect the UART clock, Peter Maydell, 2020/10/27
- [PULL 43/48] hw/char/pl011: add a clock input, Peter Maydell, 2020/10/27
- [PULL 46/48] hw/arm/sbsa-ref: add SBSA watchdog device, Peter Maydell, 2020/10/27
- [PULL 45/48] hw/watchdog: Implement SBSA watchdog device, Peter Maydell, 2020/10/27
- [PULL 48/48] hw/timer/armv7m_systick: Rewrite to use ptimers, Peter Maydell, 2020/10/27
- [PULL 47/48] hw/core/ptimer: Support ptimer being disabled by timer callback, Peter Maydell, 2020/10/27