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[PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz |
Date: |
Sat, 17 Oct 2020 16:02:26 +0200 |
The I6400 can run at 1 GHz or more. Create a 'cpuclk'
output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-19-f4bug@amsat.org>
---
hw/mips/boston.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 1b3f69e949c..cf2296f4488 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -30,6 +30,7 @@
#include "hw/mips/cps.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci-host/xilinx-pcie.h"
+#include "hw/qdev-clock.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
@@ -54,6 +55,7 @@ struct BostonState {
MachineState *mach;
MIPSCPSState cps;
SerialMM *uart;
+ Clock *cpuclk;
CharBackend lcd_display;
char lcd_content[8];
@@ -251,10 +253,19 @@ static const MemoryRegionOps boston_platreg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void mips_boston_instance_init(Object *obj)
+{
+ BostonState *s = BOSTON(obj);
+
+ s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
+ clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */
+}
+
static const TypeInfo boston_device = {
.name = TYPE_MIPS_BOSTON,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BostonState),
+ .instance_init = mips_boston_instance_init,
};
static void boston_register_types(void)
@@ -462,6 +473,8 @@ static void boston_mach_init(MachineState *machine)
&error_fatal);
object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus,
&error_fatal);
+ qdev_connect_clock_in(DEVICE(&s->cps), "clk-in",
+ qdev_get_clock_out(dev, "cpu-refclk"));
sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
--
2.26.2
- [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState, (continued)
- [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 19/44] target/mips/cpu: Make cp0_count_rate a property, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 23/44] hw/mips/fuloong2e: Set CPU frequency to 533 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 24/44] hw/mips/mipssim: Correct CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 25/44] hw/mips/jazz: Correct CPU frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 26/44] hw/mips/cps: Expose input clock and connect it to CPU cores, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz,
Philippe Mathieu-Daudé <=
- [PULL 28/44] hw/mips/malta: Set CPU frequency to 320 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 29/44] hw/mips/cps: Do not allow use without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 30/44] target/mips/cpu: Display warning when CPU is used without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 31/44] hw/mips/malta: Fix FPGA I/O region size, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 32/44] hw/mips/malta: Move gt64120 related code together, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 33/44] hw/mips/malta: Use clearer qdev style, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 34/44] hw/mips: Simplify loading 64-bit ELF kernels, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 35/44] hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 36/44] hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 37/44] hw/mips: Remove exit(1) in case of missing ROM, Philippe Mathieu-Daudé, 2020/10/17