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[PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() hel
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper |
Date: |
Sat, 17 Oct 2020 16:02:20 +0200 |
Introduce an helper to create a MIPS CPU and connect it to
a reference clock. This helper is not MIPS specific, but so
far only MIPS CPUs need it.
Suggested-by: Huacai Chen <zltjiangshi@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-13-f4bug@amsat.org>
---
target/mips/cpu.h | 12 ++++++++++++
target/mips/cpu.c | 12 ++++++++++++
2 files changed, 24 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 062a4ba6225..d41579d44ae 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1307,4 +1307,16 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState
*env, target_ulong *pc,
MIPS_HFLAG_HWRENA_ULR);
}
+/**
+ * mips_cpu_create_with_clock:
+ * @typename: a MIPS CPU type.
+ * @cpu_refclk: this cpu input clock (an output clock of another device)
+ *
+ * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk,
+ * then realizes the CPU.
+ *
+ * Returns: A #CPUState or %NULL if an error occurred.
+ */
+MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk);
+
#endif /* MIPS_CPU_H */
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 2a6f4840e20..33a9ed5c24b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -288,3 +288,15 @@ static void mips_cpu_register_types(void)
}
type_init(mips_cpu_register_types)
+
+/* Could be used by generic CPU object */
+MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
+{
+ DeviceState *cpu;
+
+ cpu = DEVICE(object_new(cpu_type));
+ qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
+ qdev_realize(cpu, NULL, &error_abort);
+
+ return MIPS_CPU(cpu);
+}
--
2.26.2
- [PULL 08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1), (continued)
- [PULL 08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 10/44] target/mips: Add loongson-ext lsdc2 group of instructions, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 13/44] target/mips/op_helper: Log unimplemented cache opcode, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 14/44] target/mips: Move cpu_mips_get_random() with CP0 helpers, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 15/44] target/mips/cp0_timer: Explicit unit in variable name, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 16/44] target/mips/cp0_timer: Document TIMER_PERIOD origin, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 19/44] target/mips/cpu: Make cp0_count_rate a property, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper,
Philippe Mathieu-Daudé <=
- [PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 23/44] hw/mips/fuloong2e: Set CPU frequency to 533 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 24/44] hw/mips/mipssim: Correct CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 25/44] hw/mips/jazz: Correct CPU frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 26/44] hw/mips/cps: Expose input clock and connect it to CPU cores, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 28/44] hw/mips/malta: Set CPU frequency to 320 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 29/44] hw/mips/cps: Do not allow use without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 30/44] target/mips/cpu: Display warning when CPU is used without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 31/44] hw/mips/malta: Fix FPGA I/O region size, Philippe Mathieu-Daudé, 2020/10/17