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[PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the C
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency |
Date: |
Sat, 17 Oct 2020 16:02:17 +0200 |
The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
---
target/mips/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 84b727fefa8..46188139b7b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -144,13 +144,13 @@ static void mips_cpu_disas_set_info(CPUState *s,
disassemble_info *info)
*/
#define CPU_FREQ_HZ_DEFAULT 200000000
#define CP0_COUNT_RATE_DEFAULT 2
-#define TIMER_PERIOD_DEFAULT 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */
static void mips_cp0_period_set(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
- env->cp0_count_ns = TIMER_PERIOD_DEFAULT;
+ env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND,
CP0_COUNT_RATE_DEFAULT,
+ CPU_FREQ_HZ_DEFAULT);
}
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
--
2.26.2
- [PULL 09/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 2), (continued)
- [PULL 09/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 2), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 11/44] target/mips/op_helper: Convert multiple if() to switch case, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 12/44] target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 10/44] target/mips: Add loongson-ext lsdc2 group of instructions, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 13/44] target/mips/op_helper: Log unimplemented cache opcode, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 14/44] target/mips: Move cpu_mips_get_random() with CP0 helpers, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 15/44] target/mips/cp0_timer: Explicit unit in variable name, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 16/44] target/mips/cp0_timer: Document TIMER_PERIOD origin, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency,
Philippe Mathieu-Daudé <=
- [PULL 19/44] target/mips/cpu: Make cp0_count_rate a property, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 23/44] hw/mips/fuloong2e: Set CPU frequency to 533 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 24/44] hw/mips/mipssim: Correct CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 25/44] hw/mips/jazz: Correct CPU frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 26/44] hw/mips/cps: Expose input clock and connect it to CPU cores, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 28/44] hw/mips/malta: Set CPU frequency to 320 MHz, Philippe Mathieu-Daudé, 2020/10/17