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[PULL 11/44] target/mips/op_helper: Convert multiple if() to switch case
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 11/44] target/mips/op_helper: Convert multiple if() to switch case |
Date: |
Sat, 17 Oct 2020 16:02:10 +0200 |
The cache operation is encoded in bits [20:18] of the instruction.
The 'op' argument of helper_cache() contains the bits [20:16].
Extract the 3 bits and parse them using a switch case. This allow
us to handle multiple cache types (the cache type is encoded in
bits [17:16]).
Previously the if() block was only checking the D-Cache (Primary
Data or Unified Primary). Now we also handle the I-Cache (Primary
Instruction), S-Cache (Secondary) and T-Cache (Terciary).
Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20200813181527.22551-2-f4bug@amsat.org>
---
target/mips/op_helper.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 9552b280e07..c15f5c07761 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1574,15 +1574,20 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
{
#ifndef CONFIG_USER_ONLY
+ uint32_t cache_operation = extract32(op, 2, 3);
target_ulong index = addr & 0x1fffffff;
- if (op == 9) {
- /* Index Store Tag */
+
+ switch (cache_operation) {
+ case 0b010: /* Index Store Tag */
memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED);
- } else if (op == 5) {
- /* Index Load Tag */
+ break;
+ case 0b001: /* Index Load Tag */
memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED);
+ break;
+ default:
+ break;
}
#endif
}
--
2.26.2
- [PULL 00/44] mips-next patches for 2020-10-17, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 01/44] util/cutils: Introduce freq_to_str() to display Hertz units, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 02/44] hw/qdev-clock: Display error hint when clock is missing from device, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 03/44] hw/core/clock: Add the clock_new helper function, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 04/44] target/mips: Fix some comment spelling errors, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 05/44] target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS>, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 06/44] target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 07/44] target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 09/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 2), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 11/44] target/mips/op_helper: Convert multiple if() to switch case,
Philippe Mathieu-Daudé <=
- [PULL 12/44] target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 10/44] target/mips: Add loongson-ext lsdc2 group of instructions, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 13/44] target/mips/op_helper: Log unimplemented cache opcode, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 14/44] target/mips: Move cpu_mips_get_random() with CP0 helpers, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 15/44] target/mips/cp0_timer: Explicit unit in variable name, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 16/44] target/mips/cp0_timer: Document TIMER_PERIOD origin, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 19/44] target/mips/cpu: Make cp0_count_rate a property, Philippe Mathieu-Daudé, 2020/10/17