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[PULL 04/44] target/mips: Fix some comment spelling errors
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 04/44] target/mips: Fix some comment spelling errors |
Date: |
Sat, 17 Oct 2020 16:02:03 +0200 |
From: zhaolichang <zhaolichang@huawei.com>
There are many spelling errors in the comments in target/mips/.
Use spellcheck to check the spelling errors.
Signed-off-by: zhaolichang <zhaolichang@huawei.com>
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/translate.c | 10 +++++-----
target/mips/translate_init.c.inc | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9230c..b811f547f38 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -188,7 +188,7 @@ static inline bool
cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
/*
* A MIPS configured with a vectorizing external interrupt controller
* will feed a vector into the Cause pending lines. The core treats
- * the status lines as a vector level, not as indiviual masks.
+ * the status lines as a vector level, not as individual masks.
*/
r = pending > status;
} else {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf72898..b4d009078e0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3718,7 +3718,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int
base, int offset,
t0 = tcg_temp_new();
addr = tcg_temp_new();
- /* compare the address against that of the preceeding LL */
+ /* compare the address against that of the preceding LL */
gen_base_offset_addr(ctx, addr, base, offset);
tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
tcg_temp_free(addr);
@@ -25597,7 +25597,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
}
/* return resulting half-words to its original position */
tcg_gen_shri_i32(t0, t0, 16);
- /* finaly update the destination */
+ /* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
tcg_temp_free(t1);
@@ -25633,7 +25633,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
}
/* return resulting half-words to its original position */
tcg_gen_shri_i32(t0, t0, 16);
- /* finaly update the destination */
+ /* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
tcg_temp_free(t1);
@@ -25702,7 +25702,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
}
/* return resulting byte to its original position */
tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
- /* finaly update the destination */
+ /* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}
@@ -25742,7 +25742,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
}
/* return resulting byte to its original position */
tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
- /* finaly update the destination */
+ /* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 637caccd890..c735b2bf667 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -995,7 +995,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t
*def)
/* MVPConf1 implemented, TLB sharable, no gating storage support,
programmable cache partitioning implemented, number of allocatable
- and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
+ and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
implemented, 5 TCs implemented. */
env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
--
2.26.2
- [PULL 00/44] mips-next patches for 2020-10-17, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 01/44] util/cutils: Introduce freq_to_str() to display Hertz units, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 02/44] hw/qdev-clock: Display error hint when clock is missing from device, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 03/44] hw/core/clock: Add the clock_new helper function, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 04/44] target/mips: Fix some comment spelling errors,
Philippe Mathieu-Daudé <=
- [PULL 05/44] target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS>, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 06/44] target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 07/44] target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 09/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 2), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 11/44] target/mips/op_helper: Convert multiple if() to switch case, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 12/44] target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 10/44] target/mips: Add loongson-ext lsdc2 group of instructions, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 13/44] target/mips/op_helper: Log unimplemented cache opcode, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 14/44] target/mips: Move cpu_mips_get_random() with CP0 helpers, Philippe Mathieu-Daudé, 2020/10/17