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[PULL 10/18] riscv/sifive_u: Add the start-in-flash property
From: |
Palmer Dabbelt |
Subject: |
[PULL 10/18] riscv/sifive_u: Add the start-in-flash property |
Date: |
Mon, 28 Oct 2019 08:48:54 -0700 |
From: Alistair Francis <address@hidden>
Add a property that when set to true QEMU will jump from the ROM code to
the start of flash memory instead of DRAM which is the default
behaviour.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 30 +++++++++++++++++++++++++++++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index eb4124f5b4..9552abf4dd 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -315,6 +315,7 @@ static void riscv_sifive_u_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
+ target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
int i;
/* Initialize SoC */
@@ -357,6 +358,10 @@ static void riscv_sifive_u_init(MachineState *machine)
}
}
+ if (s->start_in_flash) {
+ start_addr = memmap[SIFIVE_U_FLASH0].base;
+ }
+
/* reset vector */
uint32_t reset_vec[8] = {
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
@@ -369,7 +374,7 @@ static void riscv_sifive_u_init(MachineState *machine)
#endif
0x00028067, /* jr t0 */
0x00000000,
- memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
+ start_addr, /* start: .dword */
0x00000000,
/* dtb: */
};
@@ -433,8 +438,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM);
}
+static bool sifive_u_get_start_in_flash(Object *obj, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ return s->start_in_flash;
+}
+
+static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = value;
+}
+
static void riscv_sifive_u_machine_instance_init(Object *obj)
{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = false;
+ object_property_add_bool(obj, "start-in-flash",
sifive_u_get_start_in_flash,
+ sifive_u_set_start_in_flash, NULL);
+ object_property_set_description(obj, "start-in-flash",
+ "Set on to tell QEMU's ROM to jump to " \
+ "flash. Otherwise QEMU will jump to DRAM",
+ NULL);
}
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 794b958dcc..82667b5746 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -57,6 +57,8 @@ typedef struct SiFiveUState {
void *fdt;
int fdt_size;
+
+ bool start_in_flash;
} SiFiveUState;
enum {
--
2.21.0
- [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode, (continued)
- [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode, Palmer Dabbelt, 2019/10/28
- [PULL 02/18] RISC-V: Handle bus errors in the page table walker, Palmer Dabbelt, 2019/10/28
- [PULL 03/18] RISC-V: Implement cpu_do_transaction_failed, Palmer Dabbelt, 2019/10/28
- [PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node, Palmer Dabbelt, 2019/10/28
- [PULL 06/18] linux-user/riscv: Propagate fault address, Palmer Dabbelt, 2019/10/28
- [PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes, Palmer Dabbelt, 2019/10/28
- [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory, Palmer Dabbelt, 2019/10/28
- [PULL 08/18] riscv/sifive_u: Add QSPI memory region, Palmer Dabbelt, 2019/10/28
- [PULL 09/18] riscv/sifive_u: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 11/18] riscv/virt: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 10/18] riscv/sifive_u: Add the start-in-flash property,
Palmer Dabbelt <=
- [PULL 12/18] riscv/virt: Add the PFlash CFI01 device, Palmer Dabbelt, 2019/10/28
- [PULL 13/18] riscv/virt: Jump to pflash if specified, Palmer Dabbelt, 2019/10/28
- [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs, Palmer Dabbelt, 2019/10/28
- [PULL 16/18] target/riscv: Make the priv register writable by GDB, Palmer Dabbelt, 2019/10/28
- [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads, Palmer Dabbelt, 2019/10/28
- [PULL 17/18] riscv/boot: Fix possible memory leak, Palmer Dabbelt, 2019/10/28
- [PULL 18/18] target/riscv: PMP violation due to wrong size parameter, Palmer Dabbelt, 2019/10/28
- Re: [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2, Peter Maydell, 2019/10/29