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[PULL 17/18] riscv/boot: Fix possible memory leak
From: |
Palmer Dabbelt |
Subject: |
[PULL 17/18] riscv/boot: Fix possible memory leak |
Date: |
Mon, 28 Oct 2019 08:49:01 -0700 |
From: Alistair Francis <address@hidden>
Coverity (CID 1405786) thinks that there is a possible memory leak as
we don't guarantee that the memory allocated from riscv_find_firmware()
is freed. This is a false positive, but let's tidy up the code to fix
the warning.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/boot.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 2e92fb0680..7fee98d2f8 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -38,7 +38,7 @@ void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr)
{
- char *firmware_filename;
+ char *firmware_filename = NULL;
if (!machine->firmware) {
/*
@@ -70,14 +70,11 @@ void riscv_find_and_load_firmware(MachineState *machine,
* if no -bios option is set without breaking anything.
*/
firmware_filename = riscv_find_firmware(default_machine_firmware);
- } else {
- firmware_filename = machine->firmware;
- if (strcmp(firmware_filename, "none")) {
- firmware_filename = riscv_find_firmware(firmware_filename);
- }
+ } else if (strcmp(machine->firmware, "none")) {
+ firmware_filename = riscv_find_firmware(machine->firmware);
}
- if (strcmp(firmware_filename, "none")) {
+ if (firmware_filename) {
/* If not "none" load the firmware */
riscv_load_firmware(firmware_filename, firmware_load_addr);
g_free(firmware_filename);
--
2.21.0
- [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory, (continued)
- [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory, Palmer Dabbelt, 2019/10/28
- [PULL 08/18] riscv/sifive_u: Add QSPI memory region, Palmer Dabbelt, 2019/10/28
- [PULL 09/18] riscv/sifive_u: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 11/18] riscv/virt: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 10/18] riscv/sifive_u: Add the start-in-flash property, Palmer Dabbelt, 2019/10/28
- [PULL 12/18] riscv/virt: Add the PFlash CFI01 device, Palmer Dabbelt, 2019/10/28
- [PULL 13/18] riscv/virt: Jump to pflash if specified, Palmer Dabbelt, 2019/10/28
- [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs, Palmer Dabbelt, 2019/10/28
- [PULL 16/18] target/riscv: Make the priv register writable by GDB, Palmer Dabbelt, 2019/10/28
- [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads, Palmer Dabbelt, 2019/10/28
- [PULL 17/18] riscv/boot: Fix possible memory leak,
Palmer Dabbelt <=
- [PULL 18/18] target/riscv: PMP violation due to wrong size parameter, Palmer Dabbelt, 2019/10/28
- Re: [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2, Peter Maydell, 2019/10/29